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Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures
March/April 2011 (vol. 8 no. 2)
pp. 308-314
Marta Portela-García, University Carlos III of Madrid, Leganés
Celia López-Ongil, University Carlos III of Madrid, Leganés
Mario García Valderas, University Carlos III of Madrid, Leganés
Luis Entrena, University Carlos III of Madrid, Leganés
In this paper, a new fault injection approach to measure SEU sensitivity in COTS microprocessors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). This approach can be applied to most microprocessors, since JTAG standard is a widely supported interface and OCDs are usually available in current microprocessors. Hardware implementation avoids the communication between the target system and the software debugging tool, increasing significantly the fault injection efficiency. The method has been applied to a complex microprocessor (ARM). Experimental results demonstrate the approach is a fast, efficient, and cost-effective solution.

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Index Terms:
COTS microprocessors, fault injection, fault tolerance, soft errors, single event upset.
Marta Portela-García, Celia López-Ongil, Mario García Valderas, Luis Entrena, "Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures," IEEE Transactions on Dependable and Secure Computing, vol. 8, no. 2, pp. 308-314, March-April 2011, doi:10.1109/TDSC.2010.50
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