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Issue No.02 - March/April (2011 vol.8)
pp: 207-217
Piotr Zajac , CNRS, Université de Toulouse, Toulouse and Technical University of Lodz, Lodz
Mihalis Psarakis , University of Piraeus, Piraeus
Jacques Henri Collet , CNRS, Université de Toulouse, Toulouse
We study chip self-organization and fault tolerance at the architectural level to improve dependable continuous operation of multicore arrays in massively defective nanotechnologies. Architectural self-organization results from the conjunction of self-diagnosis and self-disconnection mechanisms (to identify and isolate most permanently faulty or inaccessible cores and routers), plus self-discovery of routes to maintain the communication in the array. In the methodology presented in this work, chip self-diagnosis is performed in three steps, following an ascending order of complexity: interconnects are tested first, then routers through mutual test, and cores in the last step. The mutual testing of routers is especially important as faulty routers are disconnected by good ones with no assumption on the behavior of defective elements. Moreover, the disconnection of faulty routers is not physical “"hard”) but logical (“soft”) in that a good router simply stops communicating with any adjacent router diagnosed as defective. There is no physical reconfiguration in the chip and no need for spare elements. Ultimately, the multicore array may be viewed as a black box, which incorporates protection mechanisms and self-organizes, while the external control reduces to a simple chip validation test which, in the simplest cases, reduces to counting the number of valid and accessible cores.
Multicore architectures, multiprocessors, fault diagnosis, fault tolerance, massively defective nanotechnologies.
Piotr Zajac, Mihalis Psarakis, Jacques Henri Collet, "Chip Self-Organization and Fault Tolerance in Massively Defective Multicore Arrays", IEEE Transactions on Dependable and Secure Computing, vol.8, no. 2, pp. 207-217, March/April 2011, doi:10.1109/TDSC.2009.53
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