The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.01 - January-February (2011 vol.8)
pp: 137-146
Feng Wang , Pennsylvania State University, University Park
ABSTRACT
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET models to accurately capture the nonlinear properties of submicron MOS transistors. Based on these models, we propose and validate the transient pulse generation model and propagation model for soft error rate analysis. The pulse generated by our pulse generation model matches well with that of HSPICE simulation, and the pulse propagation model provides nearly one order of magnitude improvement in accuracy over the previous models. Using these two models, we propose an accurate and efficient block-based soft error rate analysis method for combinational logic circuits.
INDEX TERMS
Reliability, simulation, fault injection, combinational logic.
CITATION
Feng Wang, "Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model", IEEE Transactions on Dependable and Secure Computing, vol.8, no. 1, pp. 137-146, January-February 2011, doi:10.1109/TDSC.2009.29
REFERENCES
[1] http://www.eas.asu.edu~ptm/, 2009.
[2] L. Anghel, D. Alexandrescu, and M. Nicolaidis, "Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy," Proc. Symp. Integrated Circuits and Systems Design, pp. 237-242, 2000.
[3] L. Anghel and M. Nicolaidis, "Cost Reduction and Evaluation of a Temporary Faults Detecting Techniques," Proc. Conf. Design Automation and Test in Europe, pp. 591-598, 2000.
[4] J.M. Cazeaux, D. Rossi, M. Omana, C. Metra, and A. Chetterjee, "On Transistor Level Gate Sizing for Increased Robustness to Transient Faults," Proc. IEEE Int'l On-Line Testing Symp., pp. 23-28, 2005.
[5] H. Cha, E.M. Rudnick, J.H. Patel, R.K. Iyer, and G.S. Choi, "A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults," IEEE Trans. Computers, vol. 45, no. 11, pp. 1248-1256, Nov. 1996.
[6] P. Dahlgren and P. Liden, "A Switch-Level Algorithm for Simulation of Transients in Combinational Logic," Proc. Int'l Fault-Tolerant Computing Symp., pp. 207-216, 1995.
[7] Y.S. Dhillon, A.U. Diril, and A. Chatterjee, "Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits," Proc. Conf. Design, Automation and Test in Europe, 2005.
[8] A. Dharchoudhury et al., "Fast Timing Simulation of Transient Fault in Digital Circuits," Proc. Int'l Conf. Computer-Aided Design, pp. 719-726, 1994.
[9] T. Shima et al., "Table Look-Up MOSFET Modeling System Using a 2-D Device Simulator and Monotonic Piecewise Cubic Interpolation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-2, no. 2, pp. 121-126, Apr. 1983.
[10] B.S. Gill, C. Papachristou, F.G. Wolff, and N. Seifert, "Node Sensitivity Analysis for Soft Errors in CMOS Logic," Proc. Int'l Test Conference (ITC), pp. 964-972, 2005.
[11] P. Hazucha and C. Svensson, "Impact of CMOS Technology Scaling on the Atmospheric Neutron Soft Error Rate," IEEE Trans. Nuclear Science, vol. 47, no. 6, pp. 2586-2594, Dec. 2000.
[12] M.A. Horowitz, "Timing Models for MOS Circuits," PhD thesis, Stanford Univ., Dec. 1983.
[13] T. Juhnke et al., "Calculation of the Soft Error Rate of Submicron CMOS Logic Circuits," IEEE J. Solid-State Circuits, vol. 30, no. 7, pp. 830-834, July 1995.
[14] Y.H. Jun, K. Jun, and S.B. Park, "An Accurate and Efficient Delay Time Modeling for MOS Logic Circuits Using Polynomial Approximation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 9, pp. 1027-1032, Sept. 1989.
[15] T. Karnik, P. Hazucha, and J. Patel, "Characterization of Soft Errors Caused by Single Event Upsets in CMOS Process," IEEE Trans. Dependable and Secure Computing, vol. 1, no. 2, pp. 128-143, Apr.-June 2004.
[16] N. Kaul, B.L. Bhuva, and S.E. Kerns, "Simulation of SEU Transients in CMOS ICs," IEEE Trans. Nuclear Science, vol. 38, no. 6, pp. 1514-1520, Dec. 1991.
[17] A.I. Kayssi, K.A. Sakallah, and T.M. Burks, "Analytical Transient Response of CMOS Inverters," IEEE Trans. Circuit and Systems, vol. 39, no. 1, pp. 42-45, Jan. 1992.
[18] S. Mitra, T. Karnik, N. Seifert, and M. Zhang, "Logic Soft Errors in Sub-65nm Technologies Design and CAD Challenges," Proc. Design Automation Conf. (DAC), June 2005.
[19] K. Mohanram, "Simulation of Transients Caused by Single-Event Upsets in Combinational Logic," Proc. Int'l Test Conf. (ITC), 2005.
[20] K. Mohanram and N.A. Touba, "Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits," Proc. Int'l Test Conf. (ITC), pp. 893-901, 2003.
[21] P.C. Murley and G.R. Srinivasan, "Soft-Error Monte Carlo Modeling Program, SEMM," IBM J. Research and Development, vol. 1, pp. 109-118, Jan. 1996.
[22] A. Nabavi-Lishi and N.C. Rumin, "Inverter Models of CMOS Gates for Supply Current and Delay Evaluation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 10, pp. 1271-1279, Oct. 1994.
[23] S. Nassif and E. Acar, "Advanced Waveform Models for nm Regime," Proc. ACM/IEEE Int'l Workshop Timing Issues, 2004.
[24] M. Omana, G. Papasso, D. Rossi, and C. Metra, "A Model for Transient Fault Propagation in Combinatorial Logic," Proc. Int'l On-Line Testing Symp., 2003.
[25] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, second ed. Prentice Hall, 2003.
[26] R. Rao, K. Chopra, D. Blaauw, and D. Sylvester, "An Efficient Static Algorithm for Soft Error Rate Analysis of Combinational Circuits," Proc. ACM/IEEE Design Automation and Test in Europe Conf. (DATE), Mar. 2006.
[27] R. Rao, K. Chopra, D. Blaauw, and D. Sylvester, "Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 3, pp. 468-479, Mar. 2007.
[28] T. Sakurai and A.R. Newton, "Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-593, Apr. 1990.
[29] P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger, and L. Alvisi, "Modeling the Effect of Technology Trends on Soft Error Rate of Combinational Logic," Proc Int'l Conf. Dependable Systems and Networks, pp. 389-398, June 2002.
[30] C. Visweswariah, K. Ravindran, K. Kalafala, S.G. Walker, and S. Narayan, "First-Order Incremental Block-Based Statistical Timing Analysis," Proc. Design Automation Conf. (DAC), pp. 331-336, June 2004.
[31] J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design, second ed. John Wiley & Sons, Inc., 1993.
[32] B. Zhang, W.S. Wang, and M. Orshansky, "FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs," Proc. Int'l Symp. Quality Electronic Design (ISQED), 2006.
[33] M. Zhang and N. Shanbhag, "A Soft Error Rate Analysis Methodology," Proc. Int'l Conf. Computer Aided Design (ICCAD), pp. 111-118, 2004.
[34] C. Zhao, X.L. Bai, and S. Dey, "A Scalable Soft Spot Analysis Methodology for Compound Noise Effects in Nano-Meter Circuits," Proc. 41st Ann. Conf. Design Automation, pp. 894-899, 2004.
[35] Q. Zhou and K. Mohanram, "Cost-Effective Radiation Hardening Technique for Logic Circuits," Proc. Int'l Conf. Computer-Aided Design, pp. 100-106, 2004.
[36] Q. Zhou and K. Mohanram, "Gate Sizing to Radiation Harden Combinational Logic," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 1, pp. 155-166, Jan. 2006.
[37] J. Ziegler, "IBM Experiments in Soft Fails in Computer Electronics," IBM J. Research and Development, vol. 1, pp. 3-18, 1996.
17 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool