CSDL Home IEEE Transactions on Dependable and Secure Computing 2010 vol.7 Issue No.03 - July-September
Issue No.03 - July-September (2010 vol.7)
Suresh Srinivasan , Intel Corp., Bangalore
Aditya Yanamandra , Pennsylvania State University, University Park
Dongkook Park , Intel Corp., Bangalore
Vijaykrishnan Narayanan , Pennsylvania State University, University Park
Chita R. Das , Pennsylvania State University, University Park
Mary J. Irwin , Pennsylvania State University, University Park
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TDSC.2008.59
The advent of diminutive technology feature sizes has led to escalating transistor densities. Burgeoning transistor counts are casting a dark shadow on modern chip design: global interconnect delays are dominating gate delays and affecting overall system performance. Networks-on-Chip (NoC) are viewed as a viable solution to this problem because of their scalability and optimized electrical properties. However, on-chip routers are susceptible to another artifact of deep submicron technology, Process Variation (PV). PV is a consequence of manufacturing imperfections, which may lead to degraded performance and even erroneous behavior. In this work, we present the first comprehensive evaluation of NoC susceptibility to PV effects, and we propose an array of architectural improvements in the form of a new router design—called SturdiSwitch—to increase resiliency to these effects. Through extensive reengineering of critical components, SturdiSwitch provides increased immunity to PV while improving performance and increasing area and power efficiency.
Fault tolerance, hardware reliability, interconnection networks, Network-on-Chip (NoC), Process Variation (PV).
Suresh Srinivasan, Aditya Yanamandra, Dongkook Park, Vijaykrishnan Narayanan, Chita R. Das, Mary J. Irwin, "On the Effects of Process Variation in Network-on-Chip Architectures", IEEE Transactions on Dependable and Secure Computing, vol.7, no. 3, pp. 240-254, July-September 2010, doi:10.1109/TDSC.2008.59