The Community for Technology Leaders
RSS Icon
Issue No.04 - October-December (2009 vol.6)
pp: 282-294
Babak Rahbaran , Vienna University of Technology, Vienna
Andreas Steininger , Vienna University of Technology, Vienna
With clock rates beyond 1 GHz, the model of a systemwide synchronous clock is becoming difficult to maintain; therefore, asynchronous design styles are increasingly receiving attention. While the traditional synchronous design style is well-proven and backed up by a rich field experience, comparatively little is known about the properties of asynchronous circuits in practical application. In the face of increased transient fault rates, robustness is a crucial property, and from a conceptual view, the so-called “delay-insensitive” asynchronous design approaches promise to be more robust than synchronous ones, since their operation does not depend on tight timing margins, and data are two-rail coded. A practical assessment of asynchronous designs in fault-injection (FI) studies, however, can rarely be found, and there is a lack of adequate methods and tools in this particular domain. Therefore, the objective of this work is 1) to provide a common approach for efficient and accurate FI in synchronous and in asynchronous designs, and 2) to experimentally compare the robustness of both synchronous and asynchronous designs. To this end, a synchronous 16-bit processor as well as its asynchronous (delay insensitive) equivalent are subjected to signal flips and delay faults. The results of over 489 million experiments are summarized and discussed, and a detailed discussion on the specific properties of the chosen asynchronous design style is given.
FIDYCO, asynchronous circuit, robustness, FPGA fault injection, delay fault.
Babak Rahbaran, Andreas Steininger, "Is Asynchronous Logic More Robust Than Synchronous Logic?", IEEE Transactions on Dependable and Secure Computing, vol.6, no. 4, pp. 282-294, October-December 2009, doi:10.1109/TDSC.2008.37
[1] International SEMATECH, International Technology Roadmap for Semiconductors, 2003.
[2] M. Delvai, W. Huber, B. Rahbaran, and A. Steininger, “An FPGA-Based Development Platform for the Virtual Real-Time Processor Component Spear,” Proc. IEEE Design and Diagnostics of Electronic Circuit and Systems Workshop (DDECS '02), pp. 98-105, 2002.
[3] B. Rahbaran, A. Steininger, and T. Handl, “Built-in Fault Injectors—The Logical Continuation of BIST?” Proc. Second IEEE Int'l Workshop Electronic Design, Test and Applications (DELTA), 2004.
[4] D.A. Huffman, “The Synthesis of Sequential Switching Circuits,” J. Franklin Inst., Mar./Apr. 1954.
[5] S.H. Unger, Asynchronous Sequential Switching Circuit. John Wiley & Sons, 1969.
[6] M. Dean, T. Williams, and D. Dill, “Efficient Self Timing with Level-Encoded 2-Phase Dual-Rail (LEDR),” Proc. MIT Conf. Advanced Research in VLSI (ARVLSI '91), technical report, 1991.
[7] A.J. McAuley, “Four State Asynchronous Architectures,” IEEE Trans. Computers, vol. 41, no. 2, pp. 129-142, Feb. 1992.
[8] I.E. Sutherland, “Micropipelines,” Comm. ACM, vol. 32, no. 6, pp.720-738, 1989.
[9] S. Pagey, S. Sherlekar, and G. Venkatesh, “Issues in Fault Modeling and Testing of Micropipelines,” Proc. First Asian Test Symp. (ATS '92), pp. 107-111, 1992.
[10] A. Khoche and E. Brunvand, “Testing Micropipelines,” Proc. Int'l Symp. Advanced Research in Asynchronous Circuit and Systems (ASYNC '94), pp. 239-246, 1994.
[11] O. Petlin and S. Furber, “Built-In Self-Testing of Micropipelines,” Proc. Int'l Symp. Advanced Research in Asynchronous Circuit and Systems (ASYNC '97), pp. 22-29, 1997.
[12] C. LaFrieda and R. Manohar, “Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits,” Proc. Int'l Conf. Dependable Systems and Networks (DSN '04), June 2004.
[13] Y. Monnet, R. Leveugle, P. Feyt, and N. Moitrel, “Practical Evaluation of Fault Countermeasures on Asynchronous DES Crypto-Processor,” Proc. 12th IEEE Int'l On-Line Testing Symp. (IOLTS '06), July 2006.
[14] Y. Monnent, M. Renaudi, and R. Leveugle, “Practical Assessment of Asynchronous Design,” Proc. 12th IEEE Int'l On-Line Testing Symp. (IOLTS), 2006.
[15] E. Normand, “Single-Event Effects in Avionics,” IEEE Trans. Nuclear Science, no. 2, pp. 461-474, 1996.
[16] E. Normand, “Single Event Upset at Ground Level,” IEEE Trans. Nuclear Science, no. 2, pp. 2742-2750, 1996.
[17] B. Rahbaran, “An Experimental Comparison of Robustness between Synchronous and Asynchronous Logic Design,” PhD thesis, Vienna Univ. of Tech nology, May 2005.
[18] K. Heragu, J.H. Patel, and V.D. Agrawal, “Segment Delay Faults: A New Fault Model,” Proc. 14th IEEE VLSI Test Symp. (VTS '96), pp. 32-39, May 1996.
[19] K. Heragu, J.H. Patel, and V.D. Agrawal, “SIGMA: A Simulator for Segment Delay Faults,” Proc. 14th IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD '96), pp. 502-508, Nov. 1996.
[20] K.M. Fant and S.A. Brandt, “NULL Convention Logic: A Complete and Consistent Logic for Asynchronous Digital Circuit Synthesis,” Proc. Int'l Conf. Application Specific Systems, Architectures and Processors (ASAP '96), Aug. 1996.
[21] M. Ligthart, K. Fant, R. Smith, A. Taubin, and A. Kondratyev, “Asynchronous Design Using Commercial HDL Synthesis Tools,” Proc. Sixth Int'l Symp. Advanced Research in Asynchronous Circuits and Systems (ASYNC '00), pp. 114-125, Apr. 2000.
[22] U. Gunneflo, J. Karlsson, and J. Torin, “Evaluation of Error Detection Schemes Using Fault Injection by Heavy-Ion Radiation,” Proc. 19th Int'l Symp. Fault-Tolerant Computing (FTCS '89), vol. 41, pp. 340-347, June 1989.
[23] J. Arlat, Y. Crouzet, J. Karlsson, and P. Folkesson, “Comparison of Physical and Software-Implemented Fault Injection Techniques,” IEEE Trans. Computer, vol. 52, no. 9, Sept. 2003.
[24] V. Sieh, O. Tschache, and F. Balbach, “VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions,” Proc. 27th Int'l Symp. Fault-Tolerant Computing (FTCS '97), pp. 32-36, 1997.
[25] P. Yuste, D. de Andreas, and L. Leumus, “INERTE: Integrated NExus-Based Real-Time Fault Injection Tool for Embedded System,” Proc. Int'l Conf. Dependable Systems and Networks (DSN '03), June 2003.
[26] J.-C. Ruiz, P. Yuste, and L.L. Pedro Gil, “On Benchmarking the Dependability of Automotive Engine Control Applications,” Proc. Int'l Conf. Dependable Systems and Networks (DSN '04), June 2004.
[27] S. Kim and A.K. Somani, “Soft Error Sensitivity Characterization for Microprocessor Dependability Enhancement Strategy,” Proc. Int'l Conf. Dependable Systems and Networks (DSN '02), June 2002.
[28] J. Guethoff and V. Sieh, “Combining Software-Implemented and Simulation-Based Fault Injection into a Single Fault Injection Method,” Proc. 25th Int'l Symp. Fault-Tolerant Computing (FTCS'95), pp. 196-206, 1995.
[29] M. Sabaratnam and O. Torbjornsen, “Evaluating the Effectiveness of Fault Tolerance in Replicated Database Management Systems,” Proc. 29th Int'l Symp. Fault-Tolerant Computing (FTCS'99), pp. 306-313, 1999.
[30] A. Steininger and C. Scherrer, “On Finding an Optimal Combination of Error Detection Mechanisms Based on Results of Fault Injection Experiments,” Proc. 27th Int'l Symp. Fault-Tolerant Computing (FTCS '97), pp. 238-247, 1997.
[31] Y. Monnet, M. Renaudin, and R. Leveugle, “Asynchronous Circuits Sensitivity to Fault Injection,” Proc. 10th IEEE Int'l On-Line Testing Symp. (IOLTS '04), pp. 121-126, July 2004.
6 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool