This Article 
 Bibliographic References 
 Add to: 
Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits
July-September 2009 (vol. 6 no. 3)
pp. 202-216
Radiation-induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to develop techniques to quickly and accurately predict soft-error rates (SERs) in combinational circuits. In this work, we present methodologies to model soft errors in both the device and logic levels. At the device level, a hierarchical methodology to model neutron-induced soft errors is proposed. This model is used to create a transient current library, which will be useful for circuit-level soft-error estimation. The library contains the transient current response to various different factors such as ion energies, operating voltage, substrate bias, angle, and location of impact. At the logic level, we propose a new approach to estimating the SER of logic circuits that attempts to capture electrical, logic, and latch window masking concurrently. The average error of the SER estimates using our approach, compared to the estimates obtained using circuit-level simulations, is 6.5 percent while providing an average speedup of 15,000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks.

[1] R. Baumann, “The Impact of Technology Scaling on Soft Error Rate Performance and Limits to the Efficacy of Error Correction,” Int'l Electron Devices Meeting Digest, pp. 329-332, 2002.
[2] M. Baze and S. Buchner, “Attenuation of Single-Event-Induced Pulses in CMOS Combinational Logic,” IEEE Trans. Nuclear Science, vol. 44, no. 6, pp. 2217-2223, 1997.
[3] S. Borkar, T. Karnik, and V. De, “Design and Reliability Challenges in Nanometer Technologies,” Proc. 41st Design Automation Conf. (DAC '04), p. 75, 2004.
[4] P.D. Bradley and E. Normand, “Single Event Upsets in Implantable Cardioverter Defibrillators,” IEEE Trans. Nuclear Science, vol. 45, pp. 2929-2940, 1998.
[5] S. Buchner, M. Baze, D. Brown, D. McMorrow, and J. Melinger, “Comparison of Error Rates in Combinational and Sequential Logic,” IEEE Trans. Nuclear Science, vol. 44, no. 6, pp. 2209-2216, 1997.
[6] K.S. Chung, T. Kim, and C.L. Lin, “G-Vector: A New Model for Glitch Analysis,” Proc. 12th Ann. IEEE Int'l ASIC/SOC Conf., pp.159-162, Sept. 1999.
[7] K. Castellani-Coulie, B. Sagnes, F. Saigne, J.-M. Palau, M.-C. Calvet, P.E. Dodd, and F.W. Sexton, “Comparison of NMOS and PMOS Transistor Sensitivity to SEU in SRAMS by Device Simulation,” IEEE Trans. Nuclear Science, vol. 50, no. 6, pp. 2239-2244, 2003.
[8] V. Degalahal, S. Cetiner, F. Alim, N. Vijaykrishnan, K. Unlu, and M.J. Irwin, “Sesee: Soft Error Simulation and Estimation Engine,” Proc. Seventh MAPLD Int'l Conf., 2004.
[9] V. Degalahal, N. Vijaykrishnan, and M.J. Irwin, “Analyzing Soft Errors in Leakage Optimized SRAM Design,” Proc. 16th Int'l Conf. VLSI Design, pp. 227-233, Jan. 2003.
[10] Y.S. Dhillon, A.U. Diril, and A. Chatterjee, “Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits,” Proc. Eighth Design, Automation and Test in Europe Conf. (DATE '05), pp.288-293, 2005.
[11] P.E. Dodd and L.W. Massengill, “Basic Mechanisms and Modeling of Single-Event Upset in Digital Microelectronics,” IEEE Trans. Nuclear Science, vol. 50, no. 3, pp. 583-602, 2003.
[12] H. Eriksson and P. Larsson-Edefors, “Glitch-Conscious Low-Power Design of Arithmetic Circuits,” Proc. Int'l Symp. Circuits and Systems (ISCAS '04), vol. 2, pp. 281-284, May 2004.
[13] S. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walstra, and C. Dai, “Impact of CMOS Process Scaling and SOI on the Soft Error Rates of Logic Processes,” Symp. VLSI Technology Digest of Technical Papers, pp. 73-74, 2001.
[14] P. Hazucha and C. Svensson, “Impact of CMOS Technology Scaling on the Atmospheric Neutron Soft Error Rate,” IEEE Trans. Nuclear Science, vol. 47, no. 6, pp. 2586-2594, 2000.
[15] S. Krishnaswamy, G.F. Viamontes, I.L. Markov, and J.P. Hayes, “Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices,” Proc. Eighth Design, Automation and Test in Europe Conf. (DATE '05), pp. 282-287, 2005.
[16] X. Liu and M.C. Papaefthymiou, “A Statistical Model of Input Glitch Propagation and Its Application in Power Macromodeling,” Proc. 45th IEEE Int'l Midwest Symp. Circuits and Systems, vol. 1, pp. 380-383, Aug. 2002.
[17] L.W. Massengill, A.E. Baranski, D.O.V. Nort, J. Meng, and B.L. Bhuva, “Analysis of Single-Event Effects in Combinational Logic: Simulation of the AM2901 Bitslice Processor,” IEEE Trans. Nuclear Science, vol. 47, no. 6, pp. 2609-2615, 2000.
[18] T.C. May and M.H. Woods, “Alpha-Particle-Induced Soft Errors in Dynamic Memories,” IEEE Trans. Electronic Devices, vol. 26, no. 1, pp. 2-9, 1979.
[19] K. Mohanram and N.A. Touba, “Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits,” Proc. Int'l Test Conf. (ITC '03), vol. 1, pp. 893-901, 2003.
[20] K. Mohanram, “Closed-Form Simulation and Robustness Models for SEU-Tolerant Design,” Proc. 23rd IEEE VLSI Test Symp., pp.327-333, May 2005.
[21] H.T. Nguyen and Y. Yagil, “A Systematic Approach to SER Estimation and Solutions,” Proc. 41st Ann. IEEE Int'l Reliability Physics Symp. (IRPS '03), pp. 60-70, Apr. 2003.
[22] M. Omana, G. Papasso, D. Rossi, and C. Metra, “A Model for Transient Fault Propagation in Combinatorial Logic,” Proc. Ninth IEEE Online Testing Symp. (IOLTS '03), pp. 111-115, July 2003.
[23] J. Palau, G. Hubert, K. Coulie, B. Sagnes, M.C. Calvet, and S. Fourtine, “Device Simulation Study of the SEU Sensitivity of SRAMS to Internal Ion Tracks Generated by Nuclear Reactions,” IEEE Trans. Nuclear Science, vol. 48, no. 2, pp.225-231, 2001.
[24] R. Rajaraman, J.S. Kim, N. Vijaykrishnan, Y. Xie, and M.J. Irwin, “SEAT-LA: A Soft Error Analysis Tool for Combinational Logic,” Proc. 19th Int'l Conf. VLSI Design, p. 4, Jan. 2006.
[25] R.R. Rao, K. Chopra, D. Blaauw, and D. Sylvester, “An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits,” Proc. Ninth Design, Automation and Test in Europe Conf. (DATE '06), pp. 164-169, Mar. 2006.
[26] T. Rejimon and S. Bhanja, “A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity,” Proc. 19th Int'l Conf. VLSI Design, p. 8, Jan. 2006.
[27] N. Seifert, D. Moyer, N. Leland, and R. Hokinson, “Historical Trend in Alpha-Particle-Induced Soft Error Rates of the Alpha Microprocessor,” Proc. 39th IEEE Ann. Int'l Reliability Physics Symp. (IRPS '01), pp. 259-265, 2001.
[28] P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi, “Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic,” Proc. Int'l Conf. Dependable Systems and Networks (DSN '02), pp. 389-398, June 2002.
[29] G.R. Srinivasan, H.K. Tang, and P.C. Murley, “Parameter-Free Predictive Modeling of Single Event Upsets Due to Protons, Neutrons, and Pions in Terrestrial Cosmic Rays,” IEEE Trans. Nuclear Science, vol. 41, pp. 2063-2070, 1994.
[30] hardware/docs/pdf816-5053-10.pdf, 2007.
[31] Y. Tosaka, H. Kanata, T. Itakura, and S. Satoh, “Simulation Technologies for Cosmic Ray Neutron-Induced Soft Errors: Models and Simulation Systems,” IEEE Trans. Nuclear Science, vol. 46, no. 3, pp. 774-780, 1999.
[32] F. Wrobel, J. Palau, M. Calvet, O. Bersillon, and H. Duarte, “Simulation of Nucleon-Induced Nuclear Reactions in a Simplified SRAM Structure: Scaling Effects on SEU and MBU Cross Sections,” IEEE Trans. Nuclear Science, vol. 48, no. 6, pp. 1946-1952, 2001.
[33] B. Zhang, W.S. Wang, and M. Orshansky, “FASER: Fast Analysis of Soft ERror Susceptibility for Cell-Based Designs,” Proc. Seventh IEEE Int'l Symp. Quality Electronic Design (ISQED '06), pp. 755-760, Mar. 2006.
[34] M. Zhang and N.R. Shanbhag, “A Soft Error Rate Analysis (SERA) Methodology,” Proc. Int'l Conf. Computer Aided Design (ICCAD'04), pp. 111-118, Nov. 2004.
[35] C. Zhao, X. Bai, and S. Dey, “A Scalable Soft Spot Analysis Methodology for Compound Noise Effects in Nano-Meter Circuits,” Proc. 41st Design Automation Conf. (DAC '04), pp.894-899, 2004.
[36] J. Ziegler, “Terrestrial Cosmic Ray Intensities,” IBM J. Research and Development, vol. 40, pp. 19-39, Jan. 1996.
[37] J.F. Ziegler and W.A. Lanford, “The Effect of Sea-Level Cosmic Rays on Electronic Devices,” IEEE Int'l Solid-State Circuits Conf. Digest of Technical Papers, vol. 23, pp. 70-71, Feb. 1980.
[38] Q. Zhou and K. Mohanram, “Gate Sizing to Radiation Harden Combinational Logic,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 1, pp. 155-166, Jan. 2006.
[39] S.V. Walstra and C. Dai, “Circuit-Level Modeling of Soft Errors in Integrated Circuits,” IEEE Trans. Device and Materials Reliability, vol. 5, no. 3, pp. 358-364, Sept. 2005.
[40] B.S. Gill, C. Papachristou, F.G. Wolff, and N. Seifert, “Node Sensitivity Analysis for Soft Errors in CMOS Logic,” Proc. IEEE Int'l Test Conf. (ITC '05), p. 9, 2005.
[41] N. Seifert, P. Slankard, M. Kirsch, B. Narasimham, V. Zia, C. Brookreson, A. Vo, S. Mitra, B. Gill, and J. Maiz, “Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices,” Proc. 44th Ann. IEEE Int'l Reliability Physics Symp. (IRPS '06), pp. 217-225, 2006.
[42] , 2007.
[43] mosfet.html, 2007.
[44] http:/, 2007.
[45] MCNP, http://mcnp-green.lanl.govindex.html, 2007.
[46] TRIM, http:/, 2007.

Index Terms:
Soft errors, modeling, Soft-Error Analysis toolset, logic, device.
Rajaraman Ramanarayanan, Vijay Degalahal, Ramakrishnan Krishnan, Jung Sub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu, "Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits," IEEE Transactions on Dependable and Secure Computing, vol. 6, no. 3, pp. 202-216, July-Sept. 2009, doi:10.1109/TDSC.2007.70231
Usage of this product signifies your acceptance of the Terms of Use.