Issue No.02 - April-June (2009 vol.6)
George Xenoulis , University of Piraeus, Piraeus
Dimitris Gizopoulos , University of Piraeus, Piraeus
Mihalis Psarakis , University of Piraeus, Piraeus
Antonis Paschalis , University of Athens, Athens
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TDSC.2008.68
Online periodic testing of microprocessors is a valuable means to increase the reliability of a low-cost system, when neither hardware nor time redundant protection schemes can be applied. This is particularly valid for floating-point (FP) units, which are becoming more common in embedded systems and are usually protected from operational faults through costly hardware redundant approaches. In this paper, we present scalable instruction-based self-test program development for both single and double precision FP units considering different instruction sets (MIPS, PowerPC, and Alpha), different microprocessor architectures (32/64-bit architectures) and different memory configurations. Moreover, we introduce bit-level manipulation instruction sequences that are essential for the development of FP unit's self-test programs. We developed self-test programs for single and double precision FP units on 32-bit and 64-bit microprocessor architectures and evaluated them with respect to the requirements of low-cost online periodic self-testing: fault coverage, memory footprint, execution time, and power consumption, assuming different memory hierarchy configurations. Our comprehensive experimental evaluations reveal that the instruction set architecture plays a significant role in the development of self-test programs. Additionally, we suggest the most suitable self-test program development approach when memory footprint or low power consumption is of paramount importance.
Online periodic testing, microprocessor self-testing.
George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis Paschalis, "Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units", IEEE Transactions on Dependable and Secure Computing, vol.6, no. 2, pp. 124-134, April-June 2009, doi:10.1109/TDSC.2008.68