This Article 
 Bibliographic References 
 Add to: 
Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units
April-June 2009 (vol. 6 no. 2)
pp. 124-134
George Xenoulis, University of Piraeus, Piraeus
Dimitris Gizopoulos, University of Piraeus, Piraeus
Mihalis Psarakis, University of Piraeus, Piraeus
Antonis Paschalis, University of Athens, Athens
Online periodic testing of microprocessors is a valuable means to increase the reliability of a low-cost system, when neither hardware nor time redundant protection schemes can be applied. This is particularly valid for floating-point (FP) units, which are becoming more common in embedded systems and are usually protected from operational faults through costly hardware redundant approaches. In this paper, we present scalable instruction-based self-test program development for both single and double precision FP units considering different instruction sets (MIPS, PowerPC, and Alpha), different microprocessor architectures (32/64-bit architectures) and different memory configurations. Moreover, we introduce bit-level manipulation instruction sequences that are essential for the development of FP unit's self-test programs. We developed self-test programs for single and double precision FP units on 32-bit and 64-bit microprocessor architectures and evaluated them with respect to the requirements of low-cost online periodic self-testing: fault coverage, memory footprint, execution time, and power consumption, assuming different memory hierarchy configurations. Our comprehensive experimental evaluations reveal that the instruction set architecture plays a significant role in the development of self-test programs. Additionally, we suggest the most suitable self-test program development approach when memory footprint or low power consumption is of paramount importance.

[1] C. Constantinescu, “Trends and Challenges in VLSI Circuit Reliability,” IEEE Micro, vol. 23, no. 4, pp. 14-19, Jul.-Aug. 2003.
[2] R. Baumann, “Soft Errors in Advanced Computer Systems,” IEEE Design & Test of Computers, vol. 22, no. 3, pp. 258-266, May-June 2005.
[3] H. Al-Asaad, B. Murray, and J. Hayes, “Online BIST for Embedded Systems,” IEEE Design & Test of Computers, vol. 15, no. 4, pp. 17-24, Oct.-Dec. 1998.
[4] K. Constantinides, O. Mutlu, T. Austin, and V. Bertacco, “Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation,” Proc. 40th Ann. IEEE/ACM Symp. Microarchitecture (MICRO), 2007.
[5] N. Oh, S. Mitra, and E. McCluskey, “ED4I: Error Detection by Diverse Data and Duplicated Instructions,” IEEE Trans. Computers, vol. 51, no. 2, pp. 180-199, Feb. 2002.
[6] J.-C. Lo, “Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands,” IEEE Trans. Computers, vol. 43, no. 4, Apr. 1994.
[7] M. Nicolaidis and Y. Zorian, “On-Line Testing for VLSI— A Compendium of Approaches,” J. Electronic Testing: Theory & Applications, vol. 12, pp. 7-20, 1998.
[8] I. Bayraktaroglu, J. Hunt, and D. Watkins, “Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues,” Proc. IEEE Int'l Test Conf. (ITC), 2006.
[9] L. Chen, S. Ravi, A. Raghunathan, and S. Dey, “A Scalable Software-Based Self-Test Methodology for Programmable Processors,” Proc. IEEE/ACM Design Automation Conf. (DAC '03), pp. 548-553, 2003.
[10] C.-P. Wen, L.-C. Wang, and K.-T. Cheng, “Simulation-Based Functional Test Generation for Embedded Processors,” IEEE Trans. Computers, vol. 55, no. 11, pp. 1335-1343, Nov. 2006.
[11] V. Singh, M. Inoue, K.K. Saluja, and H. Fujiwara, “Instruction-Based Self-Testing of Delay Faults in Pipelined Processors,” IEEE Trans. VLSI Systems, vol. 14, no. 11, pp. 1203-1215, Nov. 2006.
[12] S. Gurumurthy, S. Vasudevan, and J.A. Abraham, “Automatic Generation of Instruction Sequences Targeting Hard-to-Detect Structural Faults in a Processor,” Proc. IEEE Int'l Test Conf. (ITC), 2006.
[13] N. Kranitis, A. Paschalis, D. Gizopoulos, and G. Xenoulis, “Software-Based Self-Testing of Embedded Processors,” IEEE Trans. Computers, vol. 54, no. 4, pp. 461-475, Apr. 2005.
[14] P. Parvathala, K. Maneparambil, and W. Lindsay, “Frits— A Microprocessor Functional BIST Method,” Proc. IEEE Int'l Test Conf. (ITC '02), pp. 590-598, 2002.
[15] A. Paschalis and D. Gizopoulos, “Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors,” IEEE Trans. Computer-Aided Design Integrated Circuits Systems, vol. 24, pp. 88-99, 2005.
[16] E. Sanchez, M. Reorda, and G. Squillero, “On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors,” Proc. IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems (DFT '05), pp. 494-502, 2005.
[17] N. Kranitis, A. Merentitis, N. Laoutaris, G. Theodorou, A. Paschalis, D. Gizopoulos, and C. Halatsis, “Optimal Periodic Testing of Intermittent Faults in Embedded Pipelined Processor Applications,” Proc. IEEE/ACM Conf. Design, Automation and Test in Europe (DATE '06), pp. 65-70, 2006.
[18] IEEE, IEEE—754 Standard for Binary Floating Point Arithmetic, 1985.
[19] K. Hatayama, K. Hikone, T. Miyazaki, and H. Yamada, “A Practical Approach to Instruction-Based Test Generation for Functional Modules of VLSI Processors,” Proc. IEEE VLSI Test Symp., pp. 17-22, 1997.
[20] Intel Corp., Mobile Power Guidelines 2000.
[21] IEEE, IEEE—754 Revision Work, , 2008.
[22] G. Xenoulis, M. Psarakis, D. Gizopoulos, and A. Paschalis, “Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units,” IEEE Trans. Computers, vol. 55, no. 11, pp. 1449-1457, Nov. 2006.
[23] G. Xenoulis, M. Psarakis, D. Gizopoulos, and A. Paschalis, “On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors,” IEEE Defect and Fault-Tolerance in VLSI Systems, pp. 379-397, 2007.
[24] M. Ergegovac and T. Lang, Digital Arithmetic, chapter8, pp. 397-434. Morgan Kaufmann, 2003.
[25] FP-Library, FPLibraryindex.html, 2008.
[26] D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations,” Proc. IEEE/ACM Int'l Symp. Computer Architecture (ISCA '00), pp. 83-94, 2000.
[27] D. Burger, T. Austin, and S. Bennett, “Evaluating Future Microprocessors: The Simplescalar Toolset,” Technical Report CS-TR-1996-1308, Computer Sciences Dept., Univ. of Wisconsin-Madison, 1996.

Index Terms:
Online periodic testing, microprocessor self-testing.
George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis Paschalis, "Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units," IEEE Transactions on Dependable and Secure Computing, vol. 6, no. 2, pp. 124-134, April-June 2009, doi:10.1109/TDSC.2008.68
Usage of this product signifies your acceptance of the Terms of Use.