This Article 
 Bibliographic References 
 Add to: 
Toward Increasing FPGA Lifetime
April-June 2008 (vol. 5 no. 2)
pp. 115-127
Field Programmable Gate Arrays(FPGAs) have been aggressively moving to lower gate length technologies. Such a scaling of technology has an adverse impact on the reliability of the underlying circuits in such architectures. Various different physical phenomena have been recently explored and demonstrated to impact the reliability of circuits both in the form of transient error susceptibility and permanent failures. In this work, we analyze the impact of two different types of hard errors, namely, Time Dependent Dielectric Breakdown (TDDB) and Electro-migration (EM) on FPGAs. We also study the performance degradation of FPGAs over time caused by Hot Carrier Effects (HCE) and Negative Bias Temperature Instability (NBTI). Each such study is performed on the components of FPGAs most affected by the respective phenomena, both from performance and reliability perspective. Different solutions are demonstrated to counter each such failure and degradation phenomena to increase the operating lifetime of the FPGAs.

[1] P.K. Samudrala, J. Ramos, and S. Katkoori, “Selective Triple Modular Redundancy for SEU Mitigation in FPGAs,” Proc. Military and Aerospace Programmable Logic and Device Conf. (MAPLD '03), 2003.
[2] S. Mahapatra, V.R. Rao, B. Cheng, M. Khare, C.D. Parikh, J.C.S. Woo, and J.M. Vasi, “Performance and Hot-Carrier Reliability of 100 nm Channel Lengthjet Vapor Deposited Si3N4 MNSFETs,” IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 679-684, Apr. 2001.
[3] E. Rosenbaum, P.M. Lee, R. Moazzami, P.K. Ko, and C. Hu, “Circuit Reliability Simulator—Oxide Breakdown Module,” Int'l Electron Devices Manufacturing Technology Digest, p. 331, 1989.
[4] J.H. Stathis, “Reliability Limits for the Gate Insulator in CMOS Technology,” IBM J. Research and Development, vol. 46, 2002.
[5] Y.S. Jean and C.Y. Wu, “The Threshold-Voltage Model of MOSFET Devices with Localized Interface Charge,” IEEE Trans. Electron Devices, 1997.
[6] P. Hazucha and C. Svensson, “Impact of CMOS Technology Scaling on the Atmospheric Neutron Soft Error Rate,” IEEE Trans. Nuclear Science, vol. 47, no. 6, pp. 2586-2594, 2000.
[7] K. Kang, K. Kim, A.E. Islam, M.A. Alam, and K. Roy, “Characterization and Estimation of Circuit Reliability Degradation under NBTI Using On-Line IDDQ Measurement,” Proc. 44th Design Automation Conf. (DAC '07), pp. 358-362, 2007.
[8] W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, and Y. Cao, “The Impact of NBTI on the Performance of Combinational and Sequential Circuits,” Proc. 44th Design Automation Conf. (DAC '07), pp. 364-369, 2007.
[9] S.V. Kumar, C.H. Kim, and S.S. Sapatnekar, “Impact of NBTI on SRAM Read Stability and Design for Reliability,” Proc. Seventh Int'l Conf. Quality Electronic Design (ISQED '06), pp. 210-218, 2006.
[10] D.K. Schroder and J.F. Babcock, “Negative Bias Temperature Instability: Road to Cross in Deep Sub-Micron Silicon Semiconductor Manufacturing,” J. Applied Physics, vol. 94, pp. 1-18, 2003.
[11] J.G. Massey, “NBTI: What We Know and What We Need to Know—A Tutorial Addressing the Current Understanding and Challenges for the Future,” IEEE Int'l Integrated Reliability Workshop Final Report, pp. 199-211, 2004.
[12] J. Srinivasan, S.V. Adve, P. Bose, and J.A. Rivers, “Exploiting Structural Duplication for Lifetime Reliability Enhancement,” Proc. 32nd Ann. Int'l Symp. Computer Architecture (ISCA '05), pp.520-531, 2005.
[13] R. Vattikonda, W. Wang, and Y. Cao, “Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design,” Proc. 43rd Design Automation Conf. (DAC '06), pp. 1047-1052, 2006.
[14] M.A. Alam and S. Mahapatra, “A Comprehensive Model of PMOSNBTI Degradation,” Microelectronics Reliability, vol. 45, pp.71-81, 2005.
[15] B.C. Paul, K. Kang, H. Kufluoglu, M.A. Alam, and K. Roy, “Impact of NBTI on Temporal Performance Degradation of Digital Circuits,” Electron Device Letters, vol. 26, pp. 560-562, 2003.
[16] S.M. Alam, C.L. Gan, D.E. Troxel, and C.V. Thompson, “Circuit-Level Reliability Analysis of Cu Interconnects,” Proc. Fifth Int'l Symp. Quality Electronic Design (ISQED '04), pp. 238-243, 2004.
[17] J. Srinivasan, S.V. Adve, P. Bose, and J.A. Rivers, “The Impact of Technology Scaling on Lifetime Reliability,” Proc. Int'l Conf. Dependable Systems and Networks (DSN '04), p. 177, 2004.
[18] X. Xuan, A. Chatterjee, and A.D. Singh, “Local Redesign for Reliability of CMOS Digital Circuits under Device Degradation,” Proc. 42nd IEEE Int'l Reliability Physics Symp. (IRPS '04), pp. 651-652, 2004.
[19] F.N. Najm, “Transition Density, a Stochastic Measure of Activity in Digital Circuits,” Proc. 28th ACM/IEEE Design Automation Conf. (DAC '91), pp. 644-649, 1991.
[20] Xilinx Design Tools Page, resources design_tool, 2007.
[21] J.H. Anderson, F. Najm, and T. Tuan, “Active Leakage Power Optimization for FPGAs,” Proc. 12th ACM/SIGDA Int'l Symp. Field-Programmable Gate Arrays (FPGA '04), pp. 423-437, 2004.
[22] Critical Reliability Challenges for the Int'l Technology Roadmap for Semiconductors, Technology Transfer 03024377A-TR, Int'l Sematech, 2003.
[23] S. Srinivasan, A. Gayasen, V. Narayanan, and T. Tuan, “Leakage Control in FPGA Routing Fabric,” Proc. Asia and South Pacific Design Automation Conf. (ASPDAC '05), pp. 651-654, 2005.
[24] A. Gayasen, V. Narayanan, and M.J. Irwin, “Exploring Technology Alternatives for Nano-Scale FPGA Interconnects,” Proc. 42nd Design Automation Conf. (DAC '05), pp. 921-926, June 2005.
[25] High-K Metal Gate and Future Logic-Process Technology, , Feb. 2003.
[26] Xilinx Press Release #0470, , June 2004.
[27] E. Keller, “JRoute: A Run-Time Routing API for FPGA Hardware,” Proc. Seventh Reconfigurable Architectures Workshop (RAW '00), pp. 874-881, 2000.
[28] BPTM 65 nm: Berkeley Predictive Technology Model, 2007.
[29] V. Betz and J. Rose, “VPR: A New Packing, Placement and Routing Tool for FPGA Research,” Proc. Seventh Int'l Workshop Field-Programmable Logic and Applications (FPL '97), pp. 213-222, 1997.
[30] R. Krishnan, S. Srinivasan, V. Narayanan, M.J. Irwin, and V.S. Degalahal, “Impact of NBTI on FPGAs,” Proc. 20th Int'l Conf. VLSI Design (VLSID '07) 2007.
[31] S. Srinivasan, P. Mangalagiri, K. Sarpatwari, Y. Xie, and V. Narayanan, “FLAW:FPGA Lifetime Awareness,” Proc. 43rd Design Automation Conf. (DAC '06), 2006.
[32] W. Zhao, “New Generation of Predictive Technology Model for Sub-45 nm Design Exploration,” Proc. Seventh Int'l Conf. Quality Electronic Design (ISQED '06), 2006.
[33] Power Consumption in 65nm FPGAs, White Paper: Virtex-5 Family of FPGAs, wp246.pdf, May 2006.
[34] P. Hazucha and C. Svensson, “Impact of CMOS Technology Scaling on the Atmospheric Neutron Soft Error Rate,” IEEE Trans. Nuclear Science, vol. 47, no. 6, pp. 2586-2594, 2000.
[35] S. Srinivasan, A. Gayasen, V. Narayanan, M. Kandemir, Y. Xie, and M.J. Irwin, “Improving Soft-Error Tolerance of FPGA Configuration Bits,” Proc. Int'l Conf. Computer-Aided Design (ICCAD '04), 2004.
[36] S.A. Guccione and D. Levi, JBits: A Java-Based Interface to FPGA Hardware. Xilinx Inc., 1998.

Index Terms:
Reliability, availability, and serviceability, Reconfigurable hardware
Suresh Srinivasan, Ramakrishnan Krishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari, "Toward Increasing FPGA Lifetime," IEEE Transactions on Dependable and Secure Computing, vol. 5, no. 2, pp. 115-127, April-June 2008, doi:10.1109/TDSC.2007.70235
Usage of this product signifies your acceptance of the Terms of Use.