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Issue No.04 - October-December (2007 vol.4)
pp: 325-336
ABSTRACT
Traditionally, the only standard method of testing that has consistently provided high fault coverage has been scan test due to the high controllability and high observability this technique provides. The scan chains used in scan test not only allow test engineers to control and observe a chip, but these properties also allow the scan architecture to be used as a means to breach chip security. In this paper, we propose a technique, called Lock & Key, to neutralize the potential for scan-based side-channel attacks. It is very difficult to implement an all inclusive security strategy, but by knowing the attacker, a suitable strategy can be devised. The Lock & Key technique provides a flexible security strategy to modern designs without significant changes to scan test practices. Using this technique, the scan chains are divided into smaller subchains. With the inclusion of a test security controller, access to subchains are randomized when being accessed by an unauthorized user. Random access reduces repeatability and predictability making reverse engineering more difficult. Without proper authorization, an attacker would need to unveil several layers of security before gaining proper access to the scan chain in order to exploit it. The proposed Lock & Key technique is design independent while maintaining a relatively low area overhead.
INDEX TERMS
Security and Privacy Protection, Reliability and Testing, Scan-Based Design, Secure Design
CITATION
Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic, "Securing Designs against Scan-Based Side-Channel Attacks", IEEE Transactions on Dependable and Secure Computing, vol.4, no. 4, pp. 325-336, October-December 2007, doi:10.1109/TDSC.2007.70215
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