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A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards
October-December 2007 (vol. 4 no. 4)
pp. 245-251
ASCII Text
x 
 
M. Bucci, L. Giancane, R. Luzzi, A. Trifiletti, "A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards," IEEE Transactions on Dependable and Secure Computing, vol. 4, no. 4, pp. 245-251, October-December, 2007.
 
 
BibTex
x
 
@article{ 10.1109/TDSC.2007.70212,
author = {M. Bucci and L. Giancane and R. Luzzi and A. Trifiletti},
title = {A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards},
journal ={IEEE Transactions on Dependable and Secure Computing},
volume = {4},
number = {4},
issn = {1545-5971},
year = {2007},
pages = {245-251},
doi = {http://doi.ieeecomputersociety.org/10.1109/TDSC.2007.70212},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Dependable and Secure Computing
TI - A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards
IS - 4
SN - 1545-5971
SP245
EP251
EPD - 245-251
A1 - M. Bucci,
A1 - L. Giancane,
A1 - R. Luzzi,
A1 - A. Trifiletti,
PY - 2007
KW - differential power analysis
KW - DPA
KW - power analysis
KW - differential logic
KW - dual rail logic
KW - chip-cards
KW - cryptography
VL - 4
JA - IEEE Transactions on Dependable and Secure Computing
ER -
 
Attacks based on a differential power analysis (DPA) are a main threat when designing cryptographic functions for implementation on chip-cards. In this paper, a dynamic and differential look-up table (LUT) is presented and evaluated on a case study simulation. The proposed circuit shows a power consumption independent from the input data and can be employed to implement combinatorial functions in cryptographic processors when a high resistance against tampering is required. A typical application is the design of non-linear functions (e.g. substitution boxes) since protecting them with less expensive countermeasures (e.g. random masking) implies a significant overhead. In the adopted case study, a 1.02% spread in the power consumption has been obtained when parasitic capacitances are taken into account. Moreover, a comparison with a static CMOS implementation shows an acceptable overhead in terms of area and power consumption.

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Index Terms:
differential power analysis, DPA, power analysis, differential logic, dual rail logic, chip-cards, cryptography
Citation:
M. Bucci, L. Giancane, R. Luzzi, A. Trifiletti, "A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards," IEEE Transactions on Dependable and Secure Computing, vol. 4, no. 4, pp. 245-251, Oct.-Dec. 2007, doi:10.1109/TDSC.2007.70212
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