CSDL Home IEEE Transactions on Dependable and Secure Computing 2006 vol.3 Issue No.04 - October-December
Issue No.04 - October-December (2006 vol.3)
Zachary K. Baker , IEEE
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TDSC.2006.44
This paper presents a methodology and a tool for automatic synthesis of highly efficient intrusion detection systems using a high-level, graph-based partitioning methodology and tree-based lookahead architectures. Intrusion detection for network security is a compute-intensive application demanding high system performance. The tools implement and automate a customizable flow for the creation of efficient Field Programmable Gate Array (FPGA) architectures using system-level optimizations. Our methodology allows for customized performance through more efficient communication and extensive reuse of hardware components for dramatic increases in area-time performance.
Intrusion detection, graph algorithms, partitioning, performance, FPGA design.
Zachary K. Baker, "Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs", IEEE Transactions on Dependable and Secure Computing, vol.3, no. 4, pp. 289-300, October-December 2006, doi:10.1109/TDSC.2006.44