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A Low-Cost Concurrent BIST Scheme for Increased Dependability
April-June 2005 (vol. 2 no. 2)
pp. 150-156
ASCII Text
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Ioannis Voyiatzis, Constantin Halatsis, "A Low-Cost Concurrent BIST Scheme for Increased Dependability," IEEE Transactions on Dependable and Secure Computing, vol. 2, no. 2, pp. 150-156, April-June, 2005.
 
 
BibTex
x
 
@article{ 10.1109/TDSC.2005.16,
author = {Ioannis Voyiatzis and Constantin Halatsis},
title = {A Low-Cost Concurrent BIST Scheme for Increased Dependability},
journal ={IEEE Transactions on Dependable and Secure Computing},
volume = {2},
number = {2},
issn = {1545-5971},
year = {2005},
pages = {150-156},
doi = {http://doi.ieeecomputersociety.org/10.1109/TDSC.2005.16},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Dependable and Secure Computing
TI - A Low-Cost Concurrent BIST Scheme for Increased Dependability
IS - 2
SN - 1545-5971
SP150
EP156
EPD - 150-156
A1 - Ioannis Voyiatzis,
A1 - Constantin Halatsis,
PY - 2005
KW - Index Terms- Built-in self test
KW - concurrent testing
KW - input vector monitoring concurrent BIST.
VL - 2
JA - IEEE Transactions on Dependable and Secure Computing
ER -
 
Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes can circumvent problems appearing separately in online and in offline BIST schemes. An important measure of the quality of an input vector monitoring concurrent BIST scheme is the time required to complete the concurrent test, termed Concurrent Test Latency. In this paper, a new input vector monitoring concurrent BIST technique for combinational circuits is presented which is shown to be significantly more efficient than the input vector monitoring techniques proposed to date with respect to Concurrent Test Latency and hardware overhead trade-off, for low values of the hardware overhead.

[1] E.J. McCluskey, “Built-In Self-Test Techniques,” IEEE Design and Test of Computers, pp. 21-28, Apr. 1985.
[2] K.K. Saluja, R. Sharma, and C.R. Kime, “A Concurrent Testing Technique for Digital Circuits,” IEEE Trans. Computer-Aided Design, vol. 7, no. 12, p. 1259, Dec. 1988.
[3] K.K. Saluja, R. Sharma, and C.R. Kime, “Concurrent Comparative Testing Using BIST Resources,” Proc. Int'l Conf. Computer Aided Design, pp. 336-339, Nov. 1987.
[4] K.K. Saluja, R. Sharma, and C.R. Kime, “Concurrent Comparative Built-In Testing of Digital Circuits,” Technical Report ECE-8711, Dept. of Electrical Computer Eng., Univ. of Wisconsin, 1986.
[5] VLSI Technology, Inc., “1-Micron VSC370 Library,” Rev. 2, Apr. 1991.
[6] E. Parzen, Modern Probability Theory and Its Applications. Wiley, 1960.
[7] Y. Zorian and A. Ivanov, “An Effective BIST Scheme for ROM's,” IEEE Trans. Computers, vol. 41, no. 5, May 1992.
[8] VLSI Technology, Inc., “1-Micron Cell Compiler Library,” Rev. 2, Apr. 1991.
[9] I. Voyiatzis, A. Paschalis, D. Gizopoulos, N. Kranitis, and C. Halatsis, “A Concurrent Built-In Self-Test Architecture Based on a Self-Testing RAM,” IEEE Trans. Reliability, 2004.
[10] Y. Wu and A. Ivanov, “Single-Reference Multiple Intermediate Signature Analysis for BIST,” IEEE Trans. Computers, vol. 44, no. 6, June 1995.
[11] I. Voyiatzis, D. Nikolos, A. Paschalis, C. Halatsis, and T. Haniotakis, “An Efficient Comparative Concurrent Built-In Self Test Technique,” Proc. Fourth IEEE Asian Test Symp., pp. 309-315, Nov. 1995.
[12] J. Rajski and J. Tyszer, “Accumulator-Based Compaction of Test Responses,” IEEE Trans. Computers, vol. 42, no. 6, June 1993.
[13] M. Serra, T. Slater, J.C. Muzio, and M.D. Miller, “The Analysis of One-Dimensional Linear Cellular Automata and Their Aliasing Properties,” IEEE Trans. Computer-Aided Design, vol. 9, no. 7, pp. 767-778, July 1990.
[14] M. Damiani, P. Olivio, M. Favalli, S. Ercolani, and B. Ricco, “Aliasing in Signature Analysis Testing with Multiple Input Shift Registers,” IEEE Trans. Computer-Aided Design, vol. 9, no. 12, pp. 1344-1353, Dec. 1990.

Index Terms:
Index Terms- Built-in self test, concurrent testing, input vector monitoring concurrent BIST.
Citation:
Ioannis Voyiatzis, Constantin Halatsis, "A Low-Cost Concurrent BIST Scheme for Increased Dependability," IEEE Transactions on Dependable and Secure Computing, vol. 2, no. 2, pp. 150-156, April-June 2005, doi:10.1109/TDSC.2005.16
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