|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
| ASCII Text | x | ||
| Girish B. Ratanpal, Ronald D. Williams, Travis N. Blalock, "An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks," IEEE Transactions on Dependable and Secure Computing, vol. 1, no. 3, pp. 179-189, July-September, 2004. | |||
| BibTex | x | ||
| @article{ 10.1109/TDSC.2004.25, author = {Girish B. Ratanpal and Ronald D. Williams and Travis N. Blalock}, title = {An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks}, journal ={IEEE Transactions on Dependable and Secure Computing}, volume = {1}, number = {3}, issn = {1545-5971}, year = {2004}, pages = {179-189}, doi = {http://doi.ieeecomputersociety.org/10.1109/TDSC.2004.25}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Dependable and Secure Computing TI - An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks IS - 3 SN - 1545-5971 SP179 EP189 EPD - 179-189 A1 - Girish B. Ratanpal, A1 - Ronald D. Williams, A1 - Travis N. Blalock, PY - 2004 KW - Power analysis attacks KW - security and protection KW - smartcards KW - code breaking KW - DES KW - VLSI. VL - 1 JA - IEEE Transactions on Dependable and Secure Computing ER - | |||
[1] M. Hendry, Smart Card Security and Applications, second ed. Artech House, 2001.
[2] J. Borst, B. Preneel, and V. Rijmen, “Cryptography on Smart Cards,” Computer Networks— The Int'l J. Computer and Telecomm. Networking, vol. 36, no. 4, pp. 423-435, July 2001.
[3] P. Kocher, J. Jaffe, and B. Jun, “Differential Power Analysis,” Proc. 19th Ann. Int'l Cryptology Conf., pp. 388-397, 1999.
[4] Nat'l Bureau of Standards, “Data Encryption Standard,” Federal Information Processing Standards Publication 46, Jan. 1977.
[5] D. May, H. Muller, and N. Smart, “Non Deterministic Processors,” Proc. Sixth Australasian Conf. Information Security and Privacy (ACISP 2001), pp. 115-129, 2001.
[6] NIST, Announcing Proposed Withdrawal of Federal Information Processing Standard (FIPS) for the Data Encryption Standard (DES) and Request for Comments, Federal Register, vol. 69, no. 142, July 2004, available at http://csrc.nist.gov/Federal-registerJuly26-2004-FR-DES-Notice.pdf .
[7] S.B. Ors, F. Gurkaynak, E. Oswald, and B. Preneel, “Power-Analysis Attack on an ASIC AES Implementation,” Proc. Int'l Conf. Information Technology: Coding and Computing (ITCC 2004), vol. 2, pp. 546-552, Apr. 2004.
[8] E. Biham and A. Shamir, “Power Analysis of the Key Scheduling of the AES Candidates,” Proc. Second Advanced Encryption Standard (AES) Candidate Conf., 1999.
[9] T. Messerges, E. Dabbish, and R. Sloan, “Investigations of Power Analysis Attacks on Smartcards,” Proc. USENIX Workshop Smartcard Technology (Smartcard '99), pp. 151-161, 1999.
[10] T. Messerges, E. Dabbish, and R. Sloan, “Investigations of Power Analysis Attacks on Smartcards,” IEEE Trans. Computers, vol. 51, no. 5, May 2002.
[11] M.-L. Akkar, R. Bevan, P. Dischamp, and D. Moyart, “Power Analysis, What Is Now Possible,” Proc. Sixth Int'l Conf. the Theory and Application of Cryptology and Information Security, Advances in Cryptology (ASIACRYPT 2000), pp. 489-502, 2000.
[12] C. Clavier, J.-S. Coron, and N. Dabbous, “Differential Power Analysis in the Presence of Hardware Countermeasures,” Proc. Second Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES 2000), pp. 252-263, 2000.
[13] R. Mayer-Sommer, “Smartly Analyzing the Simplicity and the Power of Simple Power Analysis on Smartcards,” Proc. Second Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES 2000), pp. 78-92, 2000.
[14] S. Chari, C. Jutla, J. Rao, and P. Rohatgi, “Towards Sound Approaches to Counteract Power Analysis Attacks,” Proc. 19th Ann. Int'l Cryptology Conf. Advances in Cryptology (CRYPTO '99), pp. 398-412, 1999.
[15] T. Messerges, “Using Second-Order Power Analysis to Attack DPA Resistant Software,” Proc. Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES 2000), pp. 238-251, 2000.
[16] T. Messerges, “Securing the AES Finalists Against Power Analysis Attacks,” Proc. Seventh Int'l Workshop Fast Software Encryption (FSE 2000), pp. 150-164, 2001.
[17] J.-S. Coron and L. Goubin, “On Boolean and Arithmetic Masking against Differential Power Analysis,” Proc. Second Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES 2000), pp. 231-236, 2000.
[18] L. Goubin, “A Sound Method for Switching between Boolean and Arithmetic Masking,” Proc. Conf. Cryptographic Hardware and Embedded Systems (CHES 2001), pp. 3-15, 2001.
[19] M. vonWillich, “A Technique with an Information-Theoretic Basis for Protecting Secret Data from Differential Power Attacks,” Proc. Conf. Cryptography and Coding 2001, pp. 44-62, 2001.
[20] A. Shamir, “Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies,” Proc. Second Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES 2000), pp. 71-77, 2000.
[21] R. Anderson and M. Kuhn, “Tamper Resistance— A Cautionary Note,” Proc. Second USENIX Workshop Electronic Commerce, pp. 1-11, 1996.
[22] P. Rakers, L. Connell, T. Collins, and D. Russell, “Secure Contactless Smartcard ASIC with DPA Protection,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 559-565, Mar. 2001.
[23] B. Razavi, Design of Analog CMOS Integrated Circuits. New Delhi: Tata McGraw-Hill, 2002.
[24] P. Larsson, “Parasitic Resistance in a MOS Transistor Used as On-Chip Decoupling Capacitance,” IEEE J. Solid-State Circuits vol. 32, no. 4, pp. 574-76, Apr. 1997.
[25] G. Villar, E. Alarcon, F. Guinjoan, and A. Poveda, “Optimized Design of MOS Capacitors in Standard CMOS Technology and Evaluation of Their Equivalent Series Resistance for Power applications,” Proc. 2003 IEEE Int'l Symp. Circuits and Systems (ISCAS '03), pp. 451-454, May 2003.