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Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
April-June 2004 (vol. 1 no. 2)
pp. 128-143
ASCII Text
x 
 
Tanay Karnik, Peter Hazucha, Jagdish Patel, "Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes," IEEE Transactions on Dependable and Secure Computing, vol. 1, no. 2, pp. 128-143, April-June, 2004.
 
 
BibTex
x
 
@article{ 10.1109/TDSC.2004.14,
author = {Tanay Karnik and Peter Hazucha and Jagdish Patel},
title = {Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes},
journal ={IEEE Transactions on Dependable and Secure Computing},
volume = {1},
number = {2},
issn = {1545-5971},
year = {2004},
pages = {128-143},
doi = {http://doi.ieeecomputersociety.org/10.1109/TDSC.2004.14},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Dependable and Secure Computing
TI - Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IS - 2
SN - 1545-5971
SP128
EP143
EPD - 128-143
A1 - Tanay Karnik,
A1 - Peter Hazucha,
A1 - Jagdish Patel,
PY - 2004
KW - High performance
KW - error tolerance
KW - reliability
KW - soft error
KW - single event upset.
VL - 1
JA - IEEE Transactions on Dependable and Secure Computing
ER -
 
Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

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Index Terms:
High performance, error tolerance, reliability, soft error, single event upset.
Citation:
Tanay Karnik, Peter Hazucha, Jagdish Patel, "Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes," IEEE Transactions on Dependable and Secure Computing, vol. 1, no. 2, pp. 128-143, April-June 2004, doi:10.1109/TDSC.2004.14
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