CSDL Home IEEE Transactions on Pattern Analysis & Machine Intelligence 1999 vol.21 Issue No.01 - January
Issue No.01 - January (1999 vol.21)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/34.745740
<p><b>Abstract</b>—A real-time algorithm and its VLSI implementation for edge linking is presented in this paper. The linking process is based on the break points' directions and the weak level points. The proposed VLSI architecture is capable of outputting one pixel of the linked edge map per clock cycle with a latency of 11<it>n</it> + 12 clock cycles, where <it>n</it> is the number of pixel columns in the image.</p>
VLSI, edge linking, real-time image processing.
Amjad Hajjar, Tom Chen, "VLSI Architecture for Real-Time Edge Linking", IEEE Transactions on Pattern Analysis & Machine Intelligence, vol.21, no. 1, pp. 89-94, January 1999, doi:10.1109/34.745740