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VLSI Architecture for Real-Time Edge Linking
January 1999 (vol. 21 no. 1)
pp. 89-94

Abstract—A real-time algorithm and its VLSI implementation for edge linking is presented in this paper. The linking process is based on the break points' directions and the weak level points. The proposed VLSI architecture is capable of outputting one pixel of the linked edge map per clock cycle with a latency of 11n + 12 clock cycles, where n is the number of pixel columns in the image.

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Index Terms:
VLSI, edge linking, real-time image processing.
Amjad Hajjar, Tom Chen, "VLSI Architecture for Real-Time Edge Linking," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 21, no. 1, pp. 89-94, Jan. 1999, doi:10.1109/34.745740
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