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VLSI Architecture for Real-Time Edge Linking
January 1999 (vol. 21 no. 1)
pp. 89-94
ASCII Text
x 
 
Amjad Hajjar, Tom Chen, "VLSI Architecture for Real-Time Edge Linking," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 21, no. 1, pp. 89-94, January, 1999.
 
 
BibTex
x
 
@article{ 10.1109/34.745740,
author = {Amjad Hajjar and Tom Chen},
title = {VLSI Architecture for Real-Time Edge Linking},
journal ={IEEE Transactions on Pattern Analysis and Machine Intelligence},
volume = {21},
number = {1},
issn = {0162-8828},
year = {1999},
pages = {89-94},
doi = {http://doi.ieeecomputersociety.org/10.1109/34.745740},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Pattern Analysis and Machine Intelligence
TI - VLSI Architecture for Real-Time Edge Linking
IS - 1
SN - 0162-8828
SP89
EP94
EPD - 89-94
A1 - Amjad Hajjar,
A1 - Tom Chen,
PY - 1999
KW - VLSI
KW - edge linking
KW - real-time image processing.
VL - 21
JA - IEEE Transactions on Pattern Analysis and Machine Intelligence
ER -
 

Abstract—A real-time algorithm and its VLSI implementation for edge linking is presented in this paper. The linking process is based on the break points' directions and the weak level points. The proposed VLSI architecture is capable of outputting one pixel of the linked edge map per clock cycle with a latency of 11n + 12 clock cycles, where n is the number of pixel columns in the image.

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Index Terms:
VLSI, edge linking, real-time image processing.
Citation:
Amjad Hajjar, Tom Chen, "VLSI Architecture for Real-Time Edge Linking," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 21, no. 1, pp. 89-94, Jan. 1999, doi:10.1109/34.745740
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