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J. Gu, W. Wang, "A Novel Discrete Relaxation Architecture," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 14, no. 8, pp. 857865, August, 1992.  
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@article{ 10.1109/34.149596, author = {J. Gu and W. Wang}, title = {A Novel Discrete Relaxation Architecture}, journal ={IEEE Transactions on Pattern Analysis and Machine Intelligence}, volume = {14}, number = {8}, issn = {01628828}, year = {1992}, pages = {857865}, doi = {http://doi.ieeecomputersociety.org/10.1109/34.149596}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Pattern Analysis and Machine Intelligence TI  A Novel Discrete Relaxation Architecture IS  8 SN  01628828 SP857 EP865 EPD  857865 A1  J. Gu, A1  W. Wang, PY  1992 KW  discrete relaxation algorithm; sequential AC1 algorithm; time complexity; sequential AC4 algorithm; parallel DRA5 algorithm; polynomial; computational complexity; parallel algorithms; parallel architectures; polynomials VL  14 JA  IEEE Transactions on Pattern Analysis and Machine Intelligence ER   
The discrete relaxation algorithm (DRA) is a computational technique that enforces arc consistency (AC) in a constraint satisfaction problem (CSP). The original sequential AC1 algorithm suffers from O(n/sup 3/m/sup 3/) time complexity, and even the optimal sequential AC4 algorithm is O(n/sup 2/m/sup 2/) for an nobject and mlabel DRA problem. Sample problem runs show that these algorithms are all too slow to meet the need for any useful, realtime CSP applications. A parallel DRA5 algorithm that reaches a lower bound of O(nm) (where the number of processors is polynomial in the problem size) is given. A finegrained, massively parallel hardware computer architecture has been designed for the DRA5 algorithm. For practical problems, many orders of magnitude of efficiency improvement can be reached on such a hardware architecture.
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