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An Automatic Wafer Inspection System Using Pipelined Image Processing Techniques
January 1988 (vol. 10 no. 1)
pp. 4-16

An automatic wafer pattern inspection system has been developed that can detect defective patterns 6 mu m or larger in multilayered wafer patterns at a speed 30 times faster than that of a human inspector. The false-alarm rate is less than 0.5 occurrences/chip. This performance is achieved mainly by the use of a special comparison method between two adjacent patterns obtained through a single optical setup, and also by the use of digital design pattern data (CAD data). The main functions of the design pattern data are to specify the inspection area, to designate optimum parameters for inspection, and to separate defective portions into different layers, thereby facilitating the classification of the defects. All image processing is performed in one pass by a high-speed pipeline-structured image processor that can analyze an input image signal at a 7 MHz video rate.

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Index Terms:
computer vision; defect detection; defect classification; picture processing; pattern recognition; automatic wafer inspection system; pipelined image processing techniques; defective patterns; multilayered wafer patterns; false-alarm rate; comparison method; digital design pattern data; CAD data; 6 micron; 7 MHz; circuit analysis computing; computer vision; computerised pattern recognition; computerised picture processing; fault location; inspection; integrated circuit testing; pipeline processing
Citation:
H. Yoda, Y. Ohuchi, Y. Taniguchi, M. Ejiri, "An Automatic Wafer Inspection System Using Pipelined Image Processing Techniques," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 10, no. 1, pp. 4-16, Jan. 1988, doi:10.1109/34.3863
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