CSDL Home IEEE Transactions on Pattern Analysis & Machine Intelligence 1987 vol.9 Issue No.06 - June
Issue No.06 - June (1987 vol.9)
Jun Gu , Department of Computer Science, University of Utah, Salt Lake City, UT 84112.
Wei Wang , Department of Electrical Engineering, University of Utah, Salt Lake City, UT 84112.
Thomas C. Henderson , Department of Computer Science, University of Utah, Salt Lake City, UT 84112.
Discrete relaxation techniques have proven useful in solving a wide range of problems in digital signal and digital image processing, artificial intelligence, operations research, and machine vision. Much work has been devoted to finding efficient hardware architectures. This paper shows that a conventional hardware design for a Discrete Relaxation Algorithm (DRA) suffers from O(n2m3) time complexity and O(n2m2) space complexity. By reformulating DRA into a parallel computational tree and using a multiple tree-root pipelining scheme, time complexity is reduced to O(nm), while the space complexity is reduced by a factor of 2. For certain relaxation processing, the space complexity can even be decreased to O(nm). Furthermore, a technique for dynamic configuring an architectural wavefront is used which leads to an O(n) time highly concurrent DRA3 architecture.
Jun Gu, Wei Wang, Thomas C. Henderson, "A Parallel Architecture for Discrete Relaxation Algorithm", IEEE Transactions on Pattern Analysis & Machine Intelligence, vol.9, no. 6, pp. 816-831, June 1987, doi:10.1109/TPAMI.1987.4767988