CSDL Home IEEE Transactions on Pattern Analysis & Machine Intelligence 1984 vol.6 Issue No.04 - April
Issue No.04 - April (1984 vol.6)
Narendra Ahuja , Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL 61801.
This paper describes three hierarchical organizations of small processors for bottom-up image analysis:pyramids, interleaved pyramids, and pyramid trees. Progressively lower levels in the hierarchies process image windows of decreasing size. Bottom-up analysis is made feasible by transmitting up the levels quadrant borders and border-related information that captures quadrant interaction of interest for a given computation. The operation of the pyramid is illustrated by examples of standard algorithms for interior-based computations (e.g., area) and border-based computations of local properties (e.g., perimeter). A connected component counting algorithm is outlined that illustrates the role of border-related information in representing quadrant interaction. Interleaved pyramids are obtained by sharing processors among several pyramids. They increase processor utilization and throughput rate at the cost of increased hardware. Trees of shallow interleaved pyramids, calld pyramid trees, are introduced to reduce the hardware requirements of large interleaved pyramids at the expense of increased processing time, without sacrificing processor utilization. The three organizations are compared with respect to several performance measures.
Narendra Ahuja, "Multiprocessor Pyramid Architectures for Bottom-Up Image Analysis", IEEE Transactions on Pattern Analysis & Machine Intelligence, vol.6, no. 4, pp. 463-475, April 1984, doi:10.1109/TPAMI.1984.4767551