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Integrated Testing and Algorithms for Visual Inspection of Integrated Circuits
June 1983 (vol. 5 no. 6)
pp. 602-608
L. F. Pau, SENIOR MEMBER, IEEE, Centres de Recherche de Geneve, Battelle Memorial Institute, 1227 Carouge, Geneva, Switzerland.
This paper deals with the integrated pre-cap testing of integrated circuits (IC's), defined as a simultaneous combination of electrical testing and of visual inspection using image analysis techniques. The emphasis is on image analysis models and algorithms for integrated testing of small and large defects. Two algorithms are presented for the analysis of visible and infrared imagery during electrical testing. Algorithm 1 matches bridges or subgraphs derived from the topological layout. Algorithm 2 computes a figure of merit for the IC from a fuzzy language description.
Citation:
L. F. Pau, "Integrated Testing and Algorithms for Visual Inspection of Integrated Circuits," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 5, no. 6, pp. 602-608, June 1983, doi:10.1109/TPAMI.1983.4767449
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