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Computational Cost of Image Registration with a Parallel Binary Array Processor
April 1982 (vol. 4 no. 4)
pp. 449-455
A. P. Reeves, School of Electrical Engineering, Purdue University, West Lafayette, IN 47907.
A. Rostampour, School of Electrical Engineering, Purdue University, West Lafayette, IN 47907.
The application of a simulated binary array processor (BAP) to the rapid analysis of a sequence of images has been studied. Several algorithms have been developed which may be implemented on many existing parallel processing machines. The characteristic operations of a BAP are discussed and analyzed. A set of preprocessing algorithms are described which are designed to register two images of TV-type video data in real time. These algorithms illustrate the potential uses of a BAP and their cost is analyzed in detail. The results of applying these algorithms to FLIR data and to noisy optical data are given. An analysis of these algorithms illustrates the importance of an efficient global feature extraction hardware for image understanding applications.
Citation:
A. P. Reeves, A. Rostampour, "Computational Cost of Image Registration with a Parallel Binary Array Processor," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 4, no. 4, pp. 449-455, April 1982, doi:10.1109/TPAMI.1982.4767280
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