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Power Bus Signal Integrity Improvement and EMI Mitigation on Multilayer High-Speed Digital PCBs with Embedded Capacitance
October-December 2003 (vol. 2 no. 4)
pp. 314-321

Abstract—The continuous technology trend in the telecommunication market toward higher operating frequencies and high processing performances will give rise to new sophisticated chip sets, processors, and RF transceivers which will demand new features to the PCB designs. As the complexity of the integrated circuits increases, Signal Integrity (SI) and ElectroMagnetic Compatibility (EMC) become key elements in the board design process. This paper analyzes the beneficial effects that a thin dielectric material between a pair of power and ground layers (embedded capacitance) has both in reducing power bus resonance amplitudes (SI approach) and radiated emissions (EMC approach) as well. Scattering parameter measurements carried out on the power bus of two production boards are presented and correlated with the electric field strength measurements conducted on the same boards in a semianechoic chamber.

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Index Terms:
Embedded capacitance, power bus, power/ground layers, power supply decoupling, S-parameters, electric field strength.
Citation:
Vittorio Ricchiuti, "Power Bus Signal Integrity Improvement and EMI Mitigation on Multilayer High-Speed Digital PCBs with Embedded Capacitance," IEEE Transactions on Mobile Computing, vol. 2, no. 4, pp. 314-321, Oct.-Dec. 2003, doi:10.1109/TMC.2003.1255646
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