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Frequent Item Computation on a Chip
August 2011 (vol. 23 no. 8)
pp. 1169-1181
ASCII Text
x 
 
Jens Teubner, Rene Mueller, Gustavo Alonso, "Frequent Item Computation on a Chip," IEEE Transactions on Knowledge and Data Engineering, vol. 23, no. 8, pp. 1169-1181, August, 2011.
 
 
BibTex
x
 
@article{ 10.1109/TKDE.2010.216,
author = {Jens Teubner and Rene Mueller and Gustavo Alonso},
title = {Frequent Item Computation on a Chip},
journal ={IEEE Transactions on Knowledge and Data Engineering},
volume = {23},
number = {8},
issn = {1041-4347},
year = {2011},
pages = {1169-1181},
doi = {http://doi.ieeecomputersociety.org/10.1109/TKDE.2010.216},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Knowledge and Data Engineering
TI - Frequent Item Computation on a Chip
IS - 8
SN - 1041-4347
SP1169
EP1181
EPD - 1169-1181
A1 - Jens Teubner,
A1 - Rene Mueller,
A1 - Gustavo Alonso,
PY - 2011
KW - Data mining
KW - reconfigurable hardware
KW - parallelism and concurrency.
VL - 23
JA - IEEE Transactions on Knowledge and Data Engineering
ER -
 
Jens Teubner, ETH Zurich, Zurich
Rene Mueller, ETH Zurich, Zurich
Gustavo Alonso, ETH Zurich, Zurich
Computing frequent items is an important problem by itself and as a subroutine in several data mining algorithms. In this paper, we explore how to accelerate the computation of frequent items using field-programmable gate arrays (FPGAs) with a threefold goal: increase performance over existing solutions, reduce energy consumption over CPU-based systems, and explore the design space in detail as the constraints on FPGAs are very different from those of traditional software-based systems. We discuss three design alternatives, each one of them exploiting different FPGA features and each one providing different performance/scalability trade-offs. An important result of the paper is to demonstrate how the inherent massive parallelism of FPGAs can improve performance of existing algorithms but only after a fundamental redesign of the algorithms. Our experimental results show that, e.g., the pipelined solution we introduce can reach more than 100 million tuples per second of sustained throughput (four times the best available results to date) by making use of techniques that are not available to CPU-based solutions. Moreover, and unlike in software approaches, the high throughput is independent of the skew of the Zipf distribution of the input and at a far lower energy cost.

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Index Terms:
Data mining, reconfigurable hardware, parallelism and concurrency.
Citation:
Jens Teubner, Rene Mueller, Gustavo Alonso, "Frequent Item Computation on a Chip," IEEE Transactions on Knowledge and Data Engineering, vol. 23, no. 8, pp. 1169-1181, Aug. 2011, doi:10.1109/TKDE.2010.216
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