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Learning Heuristics for the Superblock Instruction Scheduling Problem
October 2009 (vol. 21 no. 10)
pp. 1489-1502
Tyrel Russell, University of Waterloo, Waterloo
Abid M. Malik, University of Waterloo, Waterloo
Michael Chase, University of Waterloo, Waterloo
Peter van Beek, University of Waterloo, Waterloo
Modern processors have multiple pipelined functional units and can issue more than one instruction per clock cycle. This places a burden on the compiler to schedule the instructions to take maximum advantage of the underlying hardware. Superblocks—a straight-line sequence of code with a single entry point and multiple possible exit points—are a commonly used scheduling region within compilers. Superblock scheduling is NP-complete, and is done suboptimally in production compilers using a greedy algorithm coupled with a heuristic. The heuristic is usually handcrafted, a potentially time-consuming process. In this paper, we show that supervised machine learning techniques can be used to semiautomate the construction of heuristics for superblock scheduling. In our approach, labeled training data were produced using an optimal superblock scheduler. A decision tree learning algorithm was then used to induce a heuristic from the training data. The automatically constructed decision tree heuristic was compared against the best previously proposed, handcrafted heuristics for superblock scheduling on the SPEC 2000 and MediaBench benchmark suites. On these benchmark suites, the decision tree heuristic reduced the number of superblocks that were not optimally scheduled by up to 38 percent, and led to improved performance on some architectural models and competitive performance on others.

[1] J.A. Fisher, “Trace Scheduling: A Technique for Global Microcode Compaction,” IEEE Trans. Computers, vol. 30, no. 7, pp. 478-490, July 1981.
[2] W.W. Hwu, S.A. Mahlke, W.Y. Chen, P.P. Chang, N.J. Warter, R.A. Bringmann, R.G. Ouellette, R.E. Hank, T. Kiyohara, G.E. Haab, J.G. Holm, and D.M. Lavery, “The Superblock: An Effective Technique for VLIW and Superscalar Compilation,” J. Supercomputing, vol. 7, no. 1, pp. 229-248, 1993.
[3] S.A. Mahlke, D.C. Lin, W.Y. Chen, R.E. Hank, and R.A. Bringmann, “Effective Compiler Support for Predicated Execution Using the Hyperblock,” Proc. 25th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro '92), pp. 45-54, 1992.
[4] J. Hennessy and T. Gross, “Postpass Code Optimization of Pipeline Constraints,” ACM Trans. Programming Languages and Systems, vol. 5, no. 3, pp. 422-448, 1983.
[5] S. Hoxey, F. Karim, B. Hay, and H. Warren, The PowerPC Compiler Writer's Guide. Warthman Assoc., 1996.
[6] A.M. Malik, T. Russell, M. Chase, and P. van Beek, “Optimal Superblock Instruction Scheduling for Multiple Issue Processors Using Constraint Programming,” Technical Report CS-2006-37, School of Computer Science, Univ. of Waterloo, 2006.
[7] J.R. Quinlan, C4.5: Programs for Machine Learning. Morgan Kaufmann, 1993.
[8] J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, third ed. Morgan Kaufmann, 2003.
[9] R. Govindarajan, “Instruction Scheduling,” The Compiler Design Handbook, Y.N. Srikant and P. Shankar, eds., pp. 631-687, CRC Press, 2003.
[10] J.E.B. Moss, P.E. Utgoff, J. Cavazos, D. Precup, D. Stefanovic, C. Brodley, and D. Scheef, “Learning to Schedule Straight-Line Code,” Proc. 10th Conf. Advances in Neural Information Processing Systems (NIPS '97), pp. 929-935, 1997.
[11] A. McGovern, J.E.B. Moss, and A.G. Barto, “Building a Basic Block Instruction Scheduler Using Reinforcement Learning and Rollouts,” Machine Learning, vol. 49, nos. 2/3, pp. 141-160, 2002.
[12] A.M. Malik, T. Russell, M. Chase, and P. van Beek, “Learning Heuristics for Basic Block Instruction Scheduling,” J. Heuristics, vol. 14, no. 6, pp. 549-569, 2008.
[13] A.M. Malik, J. McInnes, and P. van Beek, “Optimal Basic Block Instruction Scheduling for Multiple Issue Processors Using Constraint Programming,” Proc. 18th IEEE Int'l Conf. Tools with Artificial Intelligence, pp. 279-287, 2006.
[14] M. Smotherman, S. Krishnamurthy, P.S. Aravind, and D. Hunnicutt, “Efficient DAG Construction and Heuristic Calculation for Instruction Scheduling,” Proc. 24th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro '91), pp. 93-102, 1991.
[15] X. Li and S. Olafsson, “Discovering Dispatching Rules Using Data Mining,” J. Scheduling, vol. 8, pp. 515-527, 2005.
[16] C. Chekuri, R. Johnson, R. Motwani, B. Natarajan, B.R. Rau, and M. Schlansker, “Profile-Driven Instruction Level Parallel Scheduling with Application to Superblocks,” Proc. 29th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro '96), pp. 58-67, 1996.
[17] B. Deitrich and W. Hwu, “Speculative Hedge: Regulating Compile-Time Speculation against Profile Variations,” Proc. 29th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro '96), pp. 70-79, 1996.
[18] A.E. Eichenberger and W.M. Meleis, “Balance Scheduling: Weighting Branch Tradeoffs in Superblocks,” Proc. 32nd Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro '99), pp. 272-283, 1999.
[19] I.H. Witten and E. Frank, Data Mining. Morgan Kaufmann, 2000.
[20] R.A. Bringmann, “Enhancing Instruction Level Parallelism through Compiler-Controlled Speculation,” PhD dissertation, Univ. of Illinois at Urbana-Champaign, 1995.
[21] R.J. Blainey, “Instruction Scheduling in the TOBEY Compiler,” IBM J. Research and Development, vol. 38, no. 5, pp. 577-593, 1994.
[22] I. Guyon and A. Elisseeff, “An Introduction to Variable and Feature Selection,” J. Machine Learning Research, vol. 3, pp. 1157-1182, 2003.
[23] S. Muchnick, Advanced Compiler Design and Implementation. Morgan Kaufmann, 1997.
[24] L.N. Chakrapani, J. Gyllenhaal, W.W. Hwu, S.A. Mahlke, K.V. Palem, and R.M. Rabbah, “Trimaran: An Infrastructure for Research in Instruction-Level Parallelism,” Proc. 17th Int'l Workshop Languages and Compilers for High Performance Computing, pp.32-41, 2005.
[25] C. Lee, M. Potkonjak, and W. Manginoe-Smith, “MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications,” Proc. 30th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro '97), pp. 330-335, 1997.
[26] R.E. Hank, S.A. Mahlke, R.A. Bringmann, J.C. Gyllenhaal, and W.W. Hwu, “Superblock Formation Using Static Program Analysis,” Proc. 26th Ann. IEEE/ACM Int'l Symp. Microarchitecture (Micro '93), pp. 247-255, 1993.

Index Terms:
Pipeline processors, compilers, heuristics design, machine learning, constraint satisfaction.
Tyrel Russell, Abid M. Malik, Michael Chase, Peter van Beek, "Learning Heuristics for the Superblock Instruction Scheduling Problem," IEEE Transactions on Knowledge and Data Engineering, vol. 21, no. 10, pp. 1489-1502, Oct. 2009, doi:10.1109/TKDE.2009.17
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