The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.09 - September (2011 vol.17)
pp: 1337-1351
Jaroslaw (Jarek) Rossignac , Georgia Institute of Technology, Atlanta
ABSTRACT
An Expanded Boolean Expression (EBE) does not contain any XOR or EQUAL operators. The occurrence of each variable is a different literal. We provide a linear time algorithm that converts an EBE of n literals into a logically equivalent Ordered Boolean List (OBL) and show how to use the OBL to evaluate the EBE in n steps and O(log log n) space, if the values of the literals are each read once in the order prescribed by the OBL. (An evaluation workspace of 5 bits suffices for all EBEs of up to six billion literals.) The primary application is the SIMD architecture, where the same EBE is evaluated in parallel for different input vectors when rendering solid models on the GPU directly from their Constructive Solid Geometry (CSG) representation. We compare OBL to the Reduced Ordered Binary Decision Diagram (ROBDD) and suggest possible applications of OBL to logic verification and to circuit design.
INDEX TERMS
CSG, Boolean expression evaluation cost, OBDD.
CITATION
Jaroslaw (Jarek) Rossignac, "Ordered Boolean List (OBL): Reducing the Footprint for Evaluating Boolean Expressions", IEEE Transactions on Visualization & Computer Graphics, vol.17, no. 9, pp. 1337-1351, September 2011, doi:10.1109/TVCG.2010.232
REFERENCES
[1] A. Requicha and H. Voelcker, "Boolean Operations in Solid Modeling: Boundary Evaluation and Merging Algorithms," Proc. IEEE, vol. 73, no. 1, pp. 30-44, Jan. 1985.
[2] C.M. Hoffmann, Geometric and Solid Modeling: An Introduction. Morgan Kaufmann Publishers, Inc., 1989.
[3] A.G. Requicha, "Representations for Rigid Solids: Theory, Methods, and Systems," ACM Computing Surveys, vol. 12, no. 4, pp. 437-464, 1980.
[4] R. Banerjee and J.R. Rossignac, "Topologically Exact Evaluation of Polyhedra Defined in CSG with Loose Primitives," Computer Graphics Forum, vol. 15, no. 4, pp. 205-217, 1996.
[5] S. Krishnan and D. Manocha, "Efficient Representations and Techniques for Computing B-Reps of CSG Models with NURBS Primitives," Winchester, UK: Information Geometers, 1996.
[6] W.F. Bronsvoort, "Boundary Evaluation and Direct Display of CSG Models," Computer Aided Design, vol. 20, no. 7, pp. 416-419, 1988.
[7] A. Rappoport and S. Spitz, "Interactive Boolean Operations for Conceptual Design of 3D Solids," Proc. 24th Ann. Conf. Computer Graphics and Interactive Techniques, pp. 269-278, 1997.
[8] A. Sanna, P. Montuschi, A. Fisone, and B. Montrucchio, "A New Algorithm for the Rendering of CSG Scenes," Computer J., vol. 40, no. 9, pp. 555-564, 1997.
[9] N. Stewart, G. Leach, and S. John, "An Improved Z-Buffer CSG Rendering Algorithm," Proc. ACM SIGGRAPH/Eurographics Workshop Graphics Hardware, pp. 25-30, 1998.
[10] S. Kumar, S. Krishnan, D. Manocha, and A. Narkhede, "Fast Display of Complex CSG Environments," Iowa City, IA, USA: Univ. Iowa, 1995.
[11] M. Kelley, K. Gould, B. Pease, S. Winner, and A. Yen, "Hardware Accelerated Rendering of CSG and Transparency," Proc. Conf. Computer Graphics and Interactive Techniques, 1994.
[12] J.L. Ellis, G. Kedem, T.C. Lyerly, D.G. Thielman, R.J. Marisa, J.P. Menon, and H.B. Voelcker, "The Ray Casting Engine and Ray Representatives," Proc. First ACM Symp. Solid Modeling Foundations and CAD/CAM Applications, pp. 255-267, 1991.
[13] J. Goldfeather, J.P.M. Hultquist, and H. Fuchs, "Fast Constructive-Solid Geometry Display in the Pixel-Powers Graphics System," SIGGRAPH Computer Graphics, vol. 20, no. 4, pp. 107-116, 1986.
[14] J. Hable and J. Rossignac, "Blister: GPU-Based Rendering of Boolean Combinations of Free-Form Triangulated Shapes," ACM Trans. Graphics, vol. 24, no. 3, pp. 1024-1031, 2005.
[15] J. Hable and J. Rossignac, "CST: Constructive Solid Trimming for Rendering BReps and CSG Models," IEEE Trans. Visualization and Computer Graphics, vol. 13, no. 5, pp. 1004-1014, Sept./Oct. 2007.
[16] H. Biermann, D. Kristjansson, and D. Zorin, "Approximate Boolean Operations on Free-Form Solids," Proc. 28th Ann. Conf. Computer Graphics and Interactive Techniques, pp. 185-194, 2001.
[17] S. Guha, S. Krishnan, K. Munagala, and S. Venkatasubramanian, "Application of the Two-Sided Depth Test to CSG Rendering," Proc. 2003 Symp. Interactive 3D Graphics, pp. 177-180, 2003.
[18] F. Romeiro, L. Velho, and L.H.d. Figueiredo, "Computer Graphics Brazil: Scalable GPU Rendering of CSG Models," Computer Graphics, vol. 32, no. 5, pp. 526-539, 2008.
[19] C. Everitt, "Interactive Order-Independent Transparency. Nvidia Corporation," 2002.
[20] J. Rossignac, A. Megahed, and B.O. Schneider, "Interactive Inspection of Solids: Cross-Sections and Interferences," ACM SIGGRAPH, vol. 26, no. 2, pp. 353-360, 1992.
[21] J. Rossignac and J. Wu, "Correct Shading of Regularized CSG Solids Using a Depth-Interval Buffer," Proc. Eurographics Workshop Graphics Hardware, pp. 117-138, 1992.
[22] J.L. Bruno and T. Lassagne, "The Generation of Optimal Code for Stack Machines," J. ACM, vol. 22, no. 3, pp. 382-396, 1975.
[23] J. Rossignac, "Processing Disjunctive Forms Directly from CSG Graphs," Proc. CSG 94: Set-Theoretic Solid Modelling Techniques and Application, pp. 55-70, 1994.
[24] R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, vol. C-35, no. 8, pp. 671-691, Aug. 1986.
[25] R.E. Bryant, "Binary Decision Diagrams and Beyond: Enabling Technologies for Formal Verification," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, pp. 236-243, 1995.
[26] P. Ashar, A. Ghosh, and S. Devadas, "Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams," Proc. IEEE Int'l Conf. Computer Design on VLSI in Computer and Processors, pp. 259-264, 1991.
[27] Y. Matsunaga, "An Efficient Equivalence Checker for Combinational Circuits," Proc. 33rd Ann. Design Automation Conf., pp. 629-634, 1996.
[28] J. Goldfeather, S. Monar, G. Turk, and H. Fuchs, "Near Real-Time CSG Rendering Using Tree Normalization and Geometric Pruning," IEEE Computer Graphics and Applications, vol. 9, no. 3, pp. 20-28, May 1989.
[29] J. Rossignac, "Blist: A Boolean List Formulation of CSG Trees," GVU Technical Report GIT-GVU-99-04, 1998.
[30] A. Cao and C. Koh, "Non-Crossing Ordered BDD for Physical Synthesis of Regular Circuit Structure," Purdue Univ., 2003.
[31] N. Nedjah and L. de Macedo Mourelle, "Three Hardware Architectures for the Binary Modular Exponentiation: Sequential, Parallel, and Systolic," IEEE Trans. Circuits and Systems Part I, vol. 53, no. 3, pp. 627-633, Mar. 2006.
[32] J. Rossignac and A. Requicha, "Depth Buffering Display Techniques for Constructive Solid Geometry," IEEE Computer Graphics and Applications, vol. 6, no. 9, pp. 29-39, Sept. 1986.
[33] U. Cevik, "Design and Implementation of an FPGA-Based Parallel Graphics Renderer for Displaying CSG Surfaces and Volumes," Computers and Electrical Eng., vol. 30, no. 2, pp. 97-117, 2004.
[34] S. Mikami and Y. Kakazu, "A Theoretical Approach to CSG Graphics Engine," Tokyo, Japan: North-Holland, 1989.
[35] D. Salesin and J. Stolfi, "Rendering CSG Models with a ZZ-Buffer," Proc. Conf. Computer Graphics and Interactive Techniques, 1990.
[36] R. van Kleij and F. Kuijper, "A Multiprocessor System for Displaying Quadric CSG Models," Proc. Int'l Conf. Vector and Parallel Processing, 1992.
[37] B. Adams and P. Dutre, "Interactive Boolean Operations on Surfel-Bounded Solids," ACM Trans. Graphics, vol. 22, no. 3, pp. 651-656, 2003.
[38] F.W. Jansen, "Depth-Order Point Classification Techniques for CSG Display Algorithms," ACM Trans. Graphics, vol. 10, no. 1, pp. 40-70, 1990.
[39] J. Rossignac and H. Voelcker, "Active Zones in CSG for Accelerating Boundary Evaluation, Redundancy Elimination, Interference Detection, and Shading Algorithms," ACM Trans. Graphics, vol. 8, pp. 51-87, 1989.
[40] J. Rossignac, "CSG Formulations for Identifying and for Trimming Faces of CSG Models," Winchester, UK: Information Geometers, 1996.
[41] P. Dudek and P.J. Hicks, "A General-Purpose Processor-per-Pixel Analog SIMD Vision Chip," IEEE Trans. Circuits and Systems I, vol. 52, no. 1, pp. 13-20, Jan. 2005.
[42] R.E. Bryant, "Symbolic Boolean Manipulation with Ordered Binary-Decision Diagrams," ACM Computing Surveys, vol. 24, no. 3, pp. 293-318, 1992.
[43] H. Zhengdong, T. Shaopeng, and Z. Ji, "Solving CSG Equations for Checking Equivalency between Two Different Geometric Models," Computer Aided Design, vol. 36, no. 10, pp. 975-92, 2004.
[44] S. Ponzio, "A Lower Bound for Integer Multiplication with Read-Once Branching Programs," Proc. 27th Ann. ACM Symp. Theory of Computing, pp. 130-139, 1995.
[45] I. Nakata, "On Compiling Algorithms for Arithmetic Expressions," Comm. ACM, vol. 10, no. 8, pp. 492-494, 1967.
[46] W. Meyers, "Optimization of Computer Code, in Unpublished Memorandum," G. E.: Schenectady, N.Y., p. 12, 1965.
[47] R. Redziejowski, "On Arithmetic Expressions and Trees," Comm. ACM, vol. 12, no. 2, pp. 81-84, 1969.
[48] R. Sethi and J.D. Ullman, "The Generation of Optimal Code for Arithmetic Expressions," J. ACM, vol. 17, no. 4, pp. 715-728, 1970.
[49] A.V. Aho and S.C. Johnson, "Optimal Code Generation for Expression Trees," J. ACM, vol. 23, no. 3, pp. 488-501, 1976.
[50] I.K. Sethi, "Fast Sequential Evaluation of Monotonic Boolean Functions," Information Sciences, vol. 20, no. 2, pp. 101-113, 1980.
[51] R.K. Brayton, A.L. Sangiovanni-Vincentelli, C.T. McMullen, and G.D. Hachtel, Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984.
[52] S.B. Akers, "Binary Decision Diagrams," IEEE Trans. Computers, vol. C-27, no. 6, pp. 509-516, June 1978.
[53] B. Yang and D. O'Hallaron, "Parallel Breadth-First BDD Construction," Proc. Symp. Principles and Practice of Parallel Programming, pp. 145-156, 1997.
[54] Y. Breitbart, I.H. Hunt, and D. Rosenkrantz, "On the Size of Binary Decision Diagrams Representing Boolean Functions," Theoretical Computer Science, vol. 145, nos. 1/2, pp. 45-69, 1995.
[55] H. Payne and W. Meisel, "An Algorithm for Constructing Optimal Binary Decision Trees," IEEE Trans. Computers vol. C-26, no. 9, pp. 905-916, Sept. 1977.
[56] B. Bollig and I. Wegener, "Improving the Variable Ordering of OBDDs Is NP-Complete," IEEE Trans. Computers, vol. 45, no. 9, pp. 993-1002, Sept. 1996.
[57] S. Mikami and Y. Kakazu, "Development of Shaded Picture Oriented Hardware Processor for CSG Models-Formalizing the System Configuration by Set and Mapping Theories," Trans. Information Processing Soc. of Japan, vol. 30, no. 9, pp. 1240-1247, 1989.
[58] S. Mikami and Y. Kakazu, "On the Hardware Realization of CSG Ray Casting Method: Sequential Operation Method for Hardware," Trans. Information Processing Soc. of Japan, vol. 33, no. 1, pp. 46-53, 1992.
5 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool