Publication 2014 Issue No. 5 - May Abstract - CPU Scheduling for Power/Energy Management on Multicore Processors Using Cache Miss and Context Switch Data
CPU Scheduling for Power/Energy Management on Multicore Processors Using Cache Miss and Context Switch Data
May 2014 (vol. 25 no. 5)
pp. 1190-1199
 ASCII Text x Rajesh Patel, Ajoy K. Datta, "CPU Scheduling for Power/Energy Management on Multicore Processors Using Cache Miss and Context Switch Data," IEEE Transactions on Parallel and Distributed Systems, vol. 25, no. 5, pp. 1190-1199, May, 2014.
 BibTex x @article{ 10.1109/TPDS.2013.148,author = {Rajesh Patel and Ajoy K. Datta},title = {CPU Scheduling for Power/Energy Management on Multicore Processors Using Cache Miss and Context Switch Data},journal ={IEEE Transactions on Parallel and Distributed Systems},volume = {25},number = {5},issn = {1045-9219},year = {2014},pages = {1190-1199},doi = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2013.148},publisher = {IEEE Computer Society},address = {Los Alamitos, CA, USA},}
 RefWorks Procite/RefMan/Endnote x TY - JOURJO - IEEE Transactions on Parallel and Distributed SystemsTI - CPU Scheduling for Power/Energy Management on Multicore Processors Using Cache Miss and Context Switch DataIS - 5SN - 1045-9219SP1190EP1199EPD - 1190-1199A1 - Rajesh Patel, A1 - Ajoy K. Datta, PY - 2014KW - CPU migrationKW - Multicore processorKW - manycore processorKW - CPU intensive taskKW - global power budgetKW - dynamic process priorityKW - heterogeneous architectureKW - CPU frequency scaling governorKW - cpusetKW - hardware performance counterKW - dynamic CPU frequency scalingKW - memory performance saturationKW - Linux nice valueKW - cache coherenceVL - 25JA - IEEE Transactions on Parallel and Distributed SystemsER -
Rajesh Patel, Department of Computer Science, University of Nevada at Las Vegas, Las Vegas, 89154NV, USA
Ajoy K. Datta, Department of Computer Science, University of Nevada at Las Vegas, Las Vegas, NV, USA
Power and energy have become increasingly important concerns in the design and implementation of today's multicore/manycore chips. In this paper, we present two priority-based CPU scheduling algorithms, Algorithm Cache Miss Priority CPU Scheduler (${ \mmb {\cal CM}}$-PCS) and Algorithm Context Switch Priority CPU Scheduler ( ${\cal CS}$-PCS), which take advantage of often ignored dynamic performance data, in order to reduce power consumption by over 20 percent with a significant increase in performance. Our algorithms utilize Linux cpusets and cores operating at different fixed frequencies. Many other techniques, including dynamic frequency scaling, can lower a core's frequency during the execution of a non-CPU intensive task, thus lowering performance. Our algorithms match processes to cores better suited to execute those processes in an effort to lower the average completion time of all processes in an entire task, thus improving performance. They also consider a process's cache miss/cache reference ratio, number of context switches and CPU migrations, and system load. Finally, our algorithms use dynamic process priorities as scheduling criteria. We have tested our algorithms using a real AMD Opteron 6134 multicore chip and measured results directly using the “KillAWatt” meter, which samples power periodically during execution. Our results show not only a power (energy/execution time) savings of 39 watts (21.43 percent) and 38 watts (20.88 percent), but also a significant improvement in the performance, performance per watt, and execution time $\cdot$ watt (energy) for a task consisting of 24 concurrently executing benchmarks, when compared to the default Linux scheduler and CPU frequency scaling governor.
Index Terms:
CPU migration,Multicore processor,manycore processor,CPU intensive task,global power budget,dynamic process priority,heterogeneous architecture,CPU frequency scaling governor,cpuset,hardware performance counter,dynamic CPU frequency scaling,memory performance saturation,Linux nice value,cache coherence
Citation:
Rajesh Patel, Ajoy K. Datta, "CPU Scheduling for Power/Energy Management on Multicore Processors Using Cache Miss and Context Switch Data," IEEE Transactions on Parallel and Distributed Systems, vol. 25, no. 5, pp. 1190-1199, May 2014, doi:10.1109/TPDS.2013.148