Issue No.05 - May (2014 vol.25)
Smruti R. Sarangi , Department of Computer Science and Engineering, Indian Institute of Technology Delhi, New Delhi, India
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TPDS.2013.127
With an increasing number of cores per chip, it is becoming harder to guarantee optimal performance for parallel shared memory applications due to interference caused by kernel threads, interrupts, bus contention, and temperature management schemes (referred to as jitter). We demonstrate that the performance of parallel programs gets reduced (up to 35.22 percent) in large CMP based systems. In this paper, we characterize the jitter for large multi-core processors, and evaluate the loss in performance. We propose a novel jitter measurement unit that uses a distributed protocol to keep track of the number of wasted cycles. Subsequently, we try to compensate for jitter by using DVFS across a region of timing critical instructions called a frame. Additionally, we propose an OS cache that intelligently manages the OS cache lines to reduce memory interference. By performing detailed cycle accurate simulations, we show that we are able to execute a suite of Splash2 and Parsec benchmarks with a deterministic timing overhead limited to 2 percent for 14 out of 17 benchmarks with modest DVFS factors. We reduce the overall jitter by an average 13.5 percent for Splash2 and 6.4 percent for Parsec. The area overhead of our scheme is limited to 1 percent.
HPC application, CMP, hardware support for OS, DVFS, operating system jitter,
Smruti R. Sarangi, "Architectural Support for Handling Jitterin Shared Memory Based Parallel Applications", IEEE Transactions on Parallel & Distributed Systems, vol.25, no. 5, pp. 1166-1176, May 2014, doi:10.1109/TPDS.2013.127