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Multi-FPGA Accelerator for Scalable Stencil Computation with Constant Memory Bandwidth
March 2014 (vol. 25 no. 3)
pp. 695-705
Kentaro Sano, Tohoku University, Sendai
Yoshiaki Hatsuda, Kobo Co. Ltd, Kawaguchi
Satoru Yamamoto, Tohoku University, Sendai
Stencil computation is one of the important kernels in scientific computations. However, sustained performance is limited owing to restriction on memory bandwidth, especially on multicore microprocessors and graphics processing units (GPUs) because of their small operational intensity. In this paper, we present a custom computing machine (CCM), called a scalable streaming-array (SSA), for high-performance stencil computations with multiple field-programmable gate arrays (FPGAs). We design SSA based on a domain-specific programmable concept, where CCMs are programmable with the minimum functionality required for an algorithm domain. We employ a deep pipelining approach over successive iterations to achieve linear scalability for multiple devices with a constant memory bandwidth. Prototype implementation using nine FPGAs demonstrates good agreement with a performance model, and achieves 260 and 236 GFlop/s for 2D and 3D Jacobi computation, which are 87.4 and 83.9 percent of the peak, respectively, with a memory bandwidth of only 2.0 GB/s. We also evaluate the performance of SSA for state-of-the-art FPGAs.
Index Terms:
Field programmable gate arrays,Arrays,Bandwidth,Scalability,Hardware,Computational modeling,high-performance computation,Scalable streaming-array,stencil computation,custom computing machine,FPGA
Citation:
Kentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto, "Multi-FPGA Accelerator for Scalable Stencil Computation with Constant Memory Bandwidth," IEEE Transactions on Parallel and Distributed Systems, vol. 25, no. 3, pp. 695-705, March 2014, doi:10.1109/TPDS.2013.51
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