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Issue No.09 - Sept. (2013 vol.24)
pp: 1894-1907
Hao Wang , University of California, San Diego, La Jolla
Bill Lin , University of California, San Diego, La Jolla
Jun Jim Xu , Georgia Instiute of Technology, Atlanta
Statistics counters are essential in network measurement on tracking various network statistics and implementing various network counting sketches. For such applications it is crucial to maintain a large number of statistics counters at very high speeds. On the Internet with millions of flows, potentially millions of counters are required to be updated at wirespeed of 40 Gb/s and beyond. It is widely accepted that SRAM is too costly to store such large counter arrays entirely, and DRAM is too slow to catch up with the line rate. In this paper, we propose a DRAM-based architecture that takes advantage of the performance of modern commodity DRAM by interleaving counter updates to multiple memory banks. Our architecture is based on the observation that most flows on the Internet consist of multiple packets that are transmitted during a relatively short period of time, which are referred to as traffic bursts. Our proposed architecture makes use of a simple randomization scheme and a set of small fully associative request queues to statistically guarantee a near-perfect load balancing of counter updates to the memory banks. The architecture explores the benefit of traffic bursts to greatly reduce the maximum size of the request queues while providing a diminishing overflow probability guarantee. We also develop queuing models to show that as long as the flow sizes are heavy-tailed distributed due to traffic bursts, the maximum request queue length is always bounded by a small constant. The simulation results confirm the effectiveness of our queuing models. The proposed statistics counter arrays can effectively maintain line rate updates to a large number of counters while guaranteeing a diminishing overflow probability in the system.
Radiation detectors, Random access memory, Internet, Probability, Merging, Bandwidth, Emulation, queuing theory, Interleaved memories, statistics counter array, random access memories
Hao Wang, Bill Lin, Jun Jim Xu, "Robust Statistics Counter Arrays with Interleaved Memories", IEEE Transactions on Parallel & Distributed Systems, vol.24, no. 9, pp. 1894-1907, Sept. 2013, doi:10.1109/TPDS.2012.287
[1] D. Shah, S. Iyer, B. Prahhakar, and N. McKeown, "Maintaining Statistics Counters in Router Line Cards," IEEE Micro, vol. 22, no. 1, pp. 76-81, Jan./Feb. 2002.
[2] S. Ramabhadran and G. Varghese, "Efficient Implementation of a Statistics Counter Architecture," SIGMETRICS Performance Evaluation Rev., vol. 31, no. 1, pp. 261-271, 2003.
[3] Q. Zhao, J. Xu, and Z. Liu, "Design of a Novel Statistics Counter Architecture with Optimal Space and Time Efficiency," SIGMETRICS Performance Evaluation Rev., vol. 34, no. 1, pp. 323-334, 2006.
[4] Samsung, "Samsung K7S3236U4C QDRII SRAM," http:/, 2013.
[5] Samsung, "Samsung K4B4G0446A DDR3 SDRAM," http:/, 2013.
[6] M. Roeder and B. Lin, "Maintaining Exact Statistics Counters with a Multi-Level Counter Memory," Proc. IEEE GLOBECOM, vol. 2, pp. 576-581, Nov./Dec. 2004.
[7] P. Indyk, "Stable Distributions, Pseudorandom Generators, Embeddings, and Data Stream Computation," Proc. IEEE 41st Ann. Symp. Foundations Computer Science (FOCS), 2000.
[8] H. Zhao, A. Lall, M. Ogihara, O. Spatscheck, J. Wang, and J. Xu, "A Data Streaming Algorithm for Estimating Entropies of OD Flows," Proc. Seventh ACM SIGCOMM Conf. Internet Measurement (IMC), 2007.
[9] H. Zhao, H. Wang, B. Lin, and J. Xu, "Design and Performance Analysis of a Dram-Based Statistics Counter Array Architecture," Proc. ACM/IEEE Symp. Architectures for Networking and Comm. Systems (ANCS), 2009.
[10] R. Morris, "Counting Large Numbers of Events in Small Registers," Comm. ACM, vol. 21, no. 10, pp. 840-842, 1978.
[11] A. Cvetkovski, "An Algorithm for Approximate Counting Using Limited Memory Resources," SIGMETRICS Performance Evaluation Rev., vol. 35, pp. 181-190, 2007.
[12] R. Stanojevic, "Small Active Counters," Proc. IEEE INFOCOM, 2007.
[13] C. Hu, B. Liu, H. Zhao, K. Chen, Y. Chen, C. Wu, and Y. Cheng, "DISCO: Memory Efficient and Accurate Flow Statistics for Network Measurement," Proc. Int'l Conf. Distributed Computing Systems, pp. 665-674, 2010.
[14] C. Estan and G. Varghese, "New Directions in Traffic Measurement and Accounting," Proc. ACM SIGCOMM, 2002.
[15] C. Estan, K. Keys, D. Moore, and G. Varghese, "Building a Better NetFlow," Proc. ACM SIGCOMM, pp. 245-256, 2004.
[16] "Juniper Networks Solutions for Network Accounting," 350003.html, 2013.
[17] Y. Lu, A. Montanari, B. Prabhakar, S. Dharmapurikar, and A. Kabbani, "Counter Braids: A Novel Counter Architecture for Per-Flow Measurement," ACM SIGMETRICS Performance Evaluation Rev., vol. 36, pp. 121-132, 2008.
[18] N. Hua, B. Lin, J. Xu, and H. Zhao, "BRICK: A Novel Exact Active Statistics Counter Architecture," Proc. ACM/IEEE Symp. Architectures for Networking and Comm. Systems (ANCS), 2008.
[19] H. Wang, H. Zhao, B. Lin, and J. Xu, "Design and Analysis of a Robust Pipelined Memory System," Proc. IEEE INFOCOM, 2010.
[20] B. Agrawal and T. Sherwood, "High-Bandwidth Network Memory System through Virtual Pipelines," IEEE/ACM Trans. Networking, vol. 17, no. 4, pp. 1029-1041, Aug. 2009.
[21] G. Shrimali and N. McKeown, "Building Packet Buffers Using Interleaved Memories," Proc. IEEE High Performance Switching Routing Workshop (HPSR), May 2005.
[22] S. Iyer and N. Mckeown, "Designing Buffers for Router Line Cards," Technical Report TR02-HPNG-031001, Stanford Univ., Mar. 2002.
[23] H. Wang and B. Lin, "Block-Based Packet Buffer with Deterministic Packet Departures," Proc. IEEE High Performance Switching Routing Workshop (HPSR), 2010.
[24] W. Lin, S.K. Reinhardt, and D. Burger, "Reducing DRAM Latencies with an Integrated Memory Hierarchy Design," Proc. Seventh Int'l Symp. High Performance Computer Architecture, pp. 301-312, 2001.
[25] D. Patterson and J. Hennessy, Computer Architecture: A Quantitative Approach, second ed. Morgan Kaufmann, 1996.
[26] B.R. Rau, "Pseudo-Randomly Interleaved Memory," Proc. IEEE 18th Ann. Int'l Symp. Computer Architecture (ISCA), 1991.
[27] F.A. Ware and C. Hampel, "Micro-Threaded Row and Column Operations in a Dram Core," Rambus White Paper, Mar. 2005.
[28] E.H. McKinney, "Generalized Birthday Problem," Am. Math. Monthly, vol. 4, no. 73, pp. 385-387, Apr. 1966.
[29] J. Cao and K. Ramanan, "A Poisson Limit for Buffer Overflow Probabilities," Proc. IEEE INFOCOM, 2002.
[30] S. Ross, Introduction to Probability Models, ninth ed. Academic Press, 2006.
[31] A.B. Downey, "Evidence for Long-Tailed Distributions in the Internet," Proc. ACM SIGCOMM Workshop Internet Measurement, pp. 229-241, 2001.
[32] M. Garetto and D. Towsley, "Modeling, Simulation and Measurements of Queuing Delay under Long-Tail Internet Traffic," SIGMETRICS Performance Evaluation Rev., vol. 31, pp. 47-57, 2003.
[33] "XDR Datasheet," Rambus, Inc., 2002.
[34] S. Kumar, P. Crowley, and J. Turner, "Design of Randomized Multichannel Packet Storage for High Performance Routers," Proc. IEEE 13th Symp. Hot Performance Interconnects, pp. 100-106, 2005.
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