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On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip
April 2013 (vol. 24 no. 4)
pp. 767-777
Weichen Liu, Dept. of Comput. Sci. & Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong, China
Yu Wang, Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
Xuan Wang, Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China
Jiang Xu, Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China
Huazhong Yang, Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system on chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at runtime could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively predict, detect, report, and alleviate runtime threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuit-level MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.2 percent performance improvement compared with the traditional stop-go method with 1.4 percent area overhead in an 8*8-core MPSoC in 45 nm. An architecture-level cycle-accurate simulator based on SystemC is implemented to study the performance of the proposed SENoC. By applying sophisticated scheduling techniques to optimize the total system performance, a higher performance improvement of 43.5 percent is achieved for a set of real-life applications.
Index Terms:
power aware computing,circuit simulation,distributed sensors,integrated circuit design,integrated circuit noise,integrated circuit reliability,multiprocessing systems,network-on-chip,performance evaluation,total system performance optimization,on-chip sensor network,power gating-induced power-ground noise management,multiprocessor system on chip,feature size reduction,power supply voltage,processing units,MPSoC complexity,reliability threat mitigation,reliability threat monitoring,MPSoC design performance,MPSoC design scalability,MPSoC design flexibility,SENoC,reliability threat detection,information sharing,PUs,simultaneous switching noise impacts,P/G network,noise behaviors,circuit-level MPSoC P/G noise simulation,performance improvement,architecture-level cycle-accurate simulator,SystemC,Noise,Nickel,System-on-a-chip,Reliability,Switches,Integrated circuit modeling,Logic gates,system on chip,Sensor network,reliability,dynamic control,low-power,noise,power grid
Citation:
Weichen Liu, Yu Wang, Xuan Wang, Jiang Xu, Huazhong Yang, "On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip," IEEE Transactions on Parallel and Distributed Systems, vol. 24, no. 4, pp. 767-777, April 2013, doi:10.1109/TPDS.2012.193
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