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Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory
Jan. 2013 (vol. 24 no. 1)
pp. 59-71
| ASCII Text | x | ||
| Rubén Titos-Gil, Manuel E. Acacio, José M. García, "Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory," IEEE Transactions on Parallel and Distributed Systems, vol. 24, no. 1, pp. 59-71, Jan., 2013. | |||
| BibTex | x | ||
| @article{ 10.1109/TPDS.2012.103, author = {Rubén Titos-Gil and Manuel E. Acacio and José M. García}, title = {Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory}, journal ={IEEE Transactions on Parallel and Distributed Systems}, volume = {24}, number = {1}, issn = {1045-9219}, year = {2013}, pages = {59-71}, doi = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2012.103}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Parallel and Distributed Systems TI - Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory IS - 1 SN - 1045-9219 SP59 EP71 EPD - 59-71 A1 - Rubén Titos-Gil, A1 - Manuel E. Acacio, A1 - José M. García, PY - 2013 KW - Coherence KW - Protocols KW - Hardware KW - Context KW - Proposals KW - Tiles KW - Memory management KW - conflict detection KW - Parallel programming KW - multicore architectures KW - cache coherence protocols KW - transactional memory VL - 24 JA - IEEE Transactions on Parallel and Distributed Systems ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TPDS.2012.103
The efficient management of conflicts among concurrent transactions constitutes a key aspect that hardware transactional memory (HTM) systems must achieve. Scalable HTM proposals so far inherit the cache-based style of conflict detection typically found in bus-based systems, largely unaware of the interactions between transactions and directory coherence. In this paper, we demonstrate that the traditional approach of detecting conflicts at the private cache levels is inefficient when used in the context of a directory protocol. We find that the use of the directory as a mere router of coherence requests restricts the throughput of conflict detection, and show how it becomes a bottleneck under high contention. This paper proposes a scheme for conflict detection that decouples conflict detection from cache coherence in order to overcome pathological situations that degrade the performance of an eager HTM system. Our scheme places bookkeeping metadata at the directory, introducing it as a separate hardware module that leaves the coherence protocol unmodified. In comparison to a state-of-the-art eager HTM system, our design handles contention more efficiently, minimizes the performance degradation of false positives for signatures of similar hardware cost, and reduces the network traffic generated.
Index Terms:
Coherence,Protocols,Hardware,Context,Proposals,Tiles,Memory management,conflict detection,Parallel programming,multicore architectures,cache coherence protocols,transactional memory
Citation:
Rubén Titos-Gil, Manuel E. Acacio, José M. García, "Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory," IEEE Transactions on Parallel and Distributed Systems, vol. 24, no. 1, pp. 59-71, Jan. 2013, doi:10.1109/TPDS.2012.103
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