The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.12 - Dec. (2012 vol.23)
pp: 2198-2204
Honey Durga Tiwari , Konkuk University, Seoul
Huynh Ngoc Bao , Konkuk University, Seoul
Yong Beom Cho , Konkuk University, Seoul
ABSTRACT
Low-density parity check (LDPC) codes have gained much attention due to their use of various belief-propagation (BP) decoding algorithms to impart excellent error-correcting capability. The BP decoders are quite simple; however, their computation-intensive and repetitive process prohibits their use in energy-sensitive applications such as sensor networks. Bit flipping-based decoding algorithms, especially implementation-efficient, reliability ratio-based, weighted bit-flipping (IRRWBF) decoding; have shown an excellent tradeoff between error-correction performance and implementation cost. In this paper, we show that with IRRWBF, iterative re-computation can be replaced by iterative selective updating. When compared with the original algorithm, simulation results show that, decoding speed can be increased by 200 to 600 percent , as the number of decoding iterations is increased from 5 to 1,000. The decoding steps are broken down into various stages such that the update operations are mostly of the single-instruction, multiple-data (SIMD) type. In this paper, we show that by using Intel Wireless MMX 2 accelerating technology in the proposed algorithm, the speed increased by 500 to 1,500 percent. The results of implementing the proposed scheme using an Intel/Marvell PXA320 (806 MHz) CPU are presented. The proposed scheme can be used effectively in real-time LDPC codes for energy-sensitive mobile devices.
INDEX TERMS
Decoding, Iterative decoding, Wireless communication, Algorithm design and analysis, Error statistics, Data structures, Parallel processing, Parity check codes, SIMD processors, Data-parallel computing, error correcting code, low-density parity-check (LDPC) code
CITATION
Honey Durga Tiwari, Huynh Ngoc Bao, Yong Beom Cho, "A Parallel IRRWBF LDPC Decoder Based on Stream-Based Processor", IEEE Transactions on Parallel & Distributed Systems, vol.23, no. 12, pp. 2198-2204, Dec. 2012, doi:10.1109/TPDS.2012.54
REFERENCES
[1] R.G. Gallager, "Low-Density Parity-Check Codes," IEEE Trans. Information Theory, vol. 8, no. 1, pp. 21-28, Jan. 1962.
[2] F.R. Kschischang, B.J. Frey, and H.A. Loeliger, "Factor Graphs and the Sum-Product Algorithm," IEEE Trans. Information Theory, vol. 47, no. 2, pp. 498-519, Feb. 2001.
[3] J. Zhao, F. Zarkeshvari, and A. Banihashemi, "On Implementation of Min-Sum Algorithm and Its Modifications for Decoding Low-Density Parity-Check (LDPC) Codes," IEEE Trans. Comm., vol. 53, no. 4, pp. 549-554, Apr. 2005.
[4] J. Zhang and M.P.C. Fossorier, "A Modified Weighted Bit-Flipping Decoding of Low-Density Parity-Check Codes," IEEE Comm. Letters, vol. 8, no. 3, pp. 165-167, Mar. 2004.
[5] F. Guo and L. Hanzo, "Reliability Ratio Based Weighted Bit-Flipping Decoding for Low-Density Parity-Check Codes," Proc. IEE Electronics Letters, vol. 40, no. 21, pp. 1356-1358, 2004.
[6] C.H. Lee and W. Wolf, "Implementation-Efficient Reliability Ratio Based Weighted Bit-Flipping Decoding for LDPC Codes," Electronics Letters, vol. 41, pp. 1356-1358, 2005.
[7] A. Peleg and U. Weiser, "MMX Technology Extension to Intel Architecture," IEEE Micro, vol. 16, no. 4, pp. 42-50, Aug. 1996.
[8] K. Diendroff, "Pentium III = Pentium II+ SSE," Micro Processors Report, vol. 13, no. 3, pp. 6-11, Mar. 1999.
[9] L. Ruby, "Subword Parallelism in MAX-2," IEEE Micro, vol. 16, no. 4, pp. 51-59, Aug. 1996.
[10] T. Marc et al., "VIS Speeds Media Processing," IEEE Micro, vol. 16, no. 4, pp. 10-20, Aug. 1996.
[11] W. Uri et al., The Complete Guide to MMXTM Technology. Mcgraw-Hill, 1997.
[12] M.H Khan, N.C. Paver, B.A. Aldrich, and A. Hux, "Optimization Techniques for Mobile Graphics and Gaming Applications Using Intel Wireless MMX Technology," GSP, 2004.
[13] N.C. Paver et al., "Accelerating Mobile Video with Intel Wireless MMXTM Technology," Proc. IEEE Workshop Signal Processing Systems, Aug. 2003.
[14] N.C. Paver et al., "Intel Wireless MMX(TM) Technology: A 64-Bit SIMD Architecture for Mobile Multimedia," Proc. Int'l Conf. Acoustics, Speech, and Signal Processing (ICASSP), 2003.
[15] N.C. Paver, C.A. Bradley, and H.K. Moinul, Programming with Intel Wireless MMX Technology: A Developer's Guide to Mobile Multimedia Applications. Intel Press, 2004.
[16] B.A. Aldrich, N.C Paver, M.H Khan, and C.D. Emmons, "A Spatial Clustering Approach for Reduced Memory Traffic in Motion Estimation using Intel Wireless MMX Technology," Proc. Eighth World Multiconf. Systemics, Cybernetics and Informatics, July 2004.
[17] Intel XScale(R) Core Developer's Manual,
[18] X. Wu, C. Zhao, and X. You, "Parallel Weighted Bit-Flipping Decoding," IEEE Comm. Letters, vol. 11, no. 8, pp 671-673, Aug. 2007.
[19] G. Li and G. Feng, "Improved Parallel Weighted Bit-Flipping Decoding Algorithm for LDPC Codes," IET Comm., vol. 3, pp. 91-99, Jan. 2009.
[20] J. Cho, J. Kim, and W. Sung, "VLSI Implementation of a High-Throughput Soft-Bit-Flipping Decoder for Geometric LDPC Codes," IEEE Trans. Circuits Systems I, Regular Papers, vol. 57, no. 5, pp. 1083-1094, May 2010.
[21] G. Falcāo et al., "Parallel LDPC Decoding on GPUs Using a Stream-Based Computing Approach," J. Computer Science and Technology, vol. 24, no. 5, pp. 913-924, Sept. 2009.
[22] M.P.C. Fossorier, "Quasi-Cyclic Low-Density Parity-Check Codes from Circulant Permutation Matrices," IEEE Trans. Information Theory, vol. 50, no. 8, pp. 1788-1794, Aug. 2004.
[23] R. Echard and S.-C. Chang, "The Pi-Rotation Low-Density Parity Check Codes," Proc. IEEE Global Telecomm. Conf. (GLOBECOM '01), vol. 2, pp. 980-984, Nov. 2001.
[24] G. Falcao, L. Sousa, and V. Silva, "Massively LDPC Decoding on Multicore Architectures," IEEE Trans. Parallel and Distributed Systems, vol. 22, no. 2, pp. 309-322, Feb. 2011.
[25] S. Wang, S. Cheng, and Q. Wu, "A Parallel Decoding Algorithm of LDPC Codes Using CUDA," Proc. Asilomar Conf. Signals, Systems, and Computers, pp. 171-175, Oct. 2008.
[26] M. Gomes, V. Silva, C. Neves, and R. Marques, "Serial LDPC Decoding on a SIMD DSP Using Horizontal-Scheduling," Proc. 14th European Signal Processing Conf. (EUSIPCO '06), Sept. 2006.
[27] J.-Y. Lee and H.-J. Ryu, "A 1-Gb/s Flexible LDPC Decoder Supporting Multiple Code Rates and Block Lengths," IEEE Trans. Consumer Electronics, vol. 54, no. 2, pp. 417-424, May 2008.
31 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool