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Program Regularization in Memory Consistency Verification
Nov. 2012 (vol. 23 no. 11)
pp. 2163-2174
Yunji Chen, Chinese Academy of Sciences and Loongson Technologies Corporation Limited, Beijing
Lei Li, Chinese Academy of Sciences and Loongson Technologies Corporation Limited, Beijing
Tianshi Chen, Chinese Academy of Sciences and Loongson Technologies Corporation Limited, Beijing
Ling Li, Chinese Academy of Sciences and Loongson Technologies Corporation Limited, Beijing
Lei Wang, Chinese Academy of Sciences and Loongson Technologies Corporation Limited, Beijing
Xiaoxue Feng, Chinese Academy of Sciences and Loongson Technologies Corporation Limited, Beijing
Weiwu Hu, Chinese Academy of Sciences and Loongson Technologies Corporation Limited, Beijing
A widely adopted methodology for verifying the memory subsystem of a Chip Multiprocessor (CMP) is to verify executions of parallel test programs on the CMP against the given memory consistency model, which has been long known to be time consuming in both theory and practice. To accelerate memory consistency verification, previous approaches have to bear the cost of availability (e.g., relying on dedicated hardware supports that have not been offered by many commodity CMPs) or completeness (e.g., missing some bugs). In the meantime, the impact of parallel programs on memory consistency verification has more or less been overlooked. One piece of evidence is that few investigations have been dedicated to finding appropriate test programs enabling more efficient verification From a novel perspective of test program, we devise a practical technique called “program regularization,” which can effectively reduce the computation time of memory consistency verification. The key intuition behind program regularization is that any parallel program, if being reformed appropriately, can enable efficient memory consistency verification. More specifically, for an original program, program regularization introduces some auxiliary memory addresses, and periodically inserts load/store operations accessing these addresses to the original program. With the regularized program, memory consistency verification can be accomplished in linear time (with respect to the number of memory operations) when the number of processors is fixed. Experimental results show that program regularization can significantly accelerate memory consistency verification. Last but not least, our technique, which does not rely on concrete verification algorithm or dedicated hardware support, can be smoothly integrated into existing presilicon/postsilicon verification platforms of industrial CMPs to speed up memory consistency verification.
Index Terms:
Program processors,Law,Complexity theory,Memory management,Receivers,Hardware,VSC-read,Memory consistency verification,frontier graph,parallel program,program regularization
Citation:
Yunji Chen, Lei Li, Tianshi Chen, Ling Li, Lei Wang, Xiaoxue Feng, Weiwu Hu, "Program Regularization in Memory Consistency Verification," IEEE Transactions on Parallel and Distributed Systems, vol. 23, no. 11, pp. 2163-2174, Nov. 2012, doi:10.1109/TPDS.2012.44
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