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Optimizing Techniques for Parallel Digital Logic Simulation
June 2012 (vol. 23 no. 6)
pp. 1135-1146
ASCII Text
x 
 
Sina Meraji, Carl Tropper, "Optimizing Techniques for Parallel Digital Logic Simulation," IEEE Transactions on Parallel and Distributed Systems, vol. 23, no. 6, pp. 1135-1146, June, 2012.
 
 
BibTex
x
 
@article{ 10.1109/TPDS.2011.246,
author = {Sina Meraji and Carl Tropper},
title = {Optimizing Techniques for Parallel Digital Logic Simulation},
journal ={IEEE Transactions on Parallel and Distributed Systems},
volume = {23},
number = {6},
issn = {1045-9219},
year = {2012},
pages = {1135-1146},
doi = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2011.246},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Parallel and Distributed Systems
TI - Optimizing Techniques for Parallel Digital Logic Simulation
IS - 6
SN - 1045-9219
SP1135
EP1146
EPD - 1135-1146
A1 - Sina Meraji,
A1 - Carl Tropper,
PY - 2012
KW - Parallel digital logic simulation
KW - Verilog
KW - dynamic load balancing
KW - Q-learning
KW - simulated annealing
KW - time warp.
VL - 23
JA - IEEE Transactions on Parallel and Distributed Systems
ER -
 
Sina Meraji, McGill University, Montreal
Carl Tropper, McGill University, Montreal
A major part of the design process for Integrated Circuits (IC) is the process of circuit verification, in which the correctness of a circuit's design is evaluated. Discrete event simulation is a central tool in this effort. As proscribed by Moore's law, the number of transistors which can be placed on an IC doubles every 18 months. As a result, simulation has become the major bottleneck in the circuit design process. To alleviate this difficulty, it is possible to make use of parallel (or distributed) circuit simulation. In this paper, we make use of a parallel gate-level simulator which we developed and which is based upon Time Warp. Gate-level simulations exhibit two characteristics which can easily result in either instability or severely degraded simulation performance. Because of the low computational granularity of a gate-level simulation and because the computational load varies throughout the course of the simulation, the performance of Time Warp can be either severely degraded or be unstable. Restraining the optimism of Time Warp via a bounded window and utilizing dynamic load balancing are approaches to deal with these difficulties. In this paper, we make use of learning techniques from artificial intelligence (multiagent Q-learning, simulated annealing) to develop a combined bounded window and dynamic load balancing algorithm for parallel digital logic simulation. We evaluated the performance of these algorithms on open source Sparc and Leon designs and on two Viterbi decoder designs. We observed up to 60 percent improvement in simulation time of one of the decoders using this approach.

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Index Terms:
Parallel digital logic simulation, Verilog, dynamic load balancing, Q-learning, simulated annealing, time warp.
Citation:
Sina Meraji, Carl Tropper, "Optimizing Techniques for Parallel Digital Logic Simulation," IEEE Transactions on Parallel and Distributed Systems, vol. 23, no. 6, pp. 1135-1146, June 2012, doi:10.1109/TPDS.2011.246
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