Subscribe

Issue No.06 - June (2012 vol.23)

pp: 1135-1146

Sina Meraji , McGill University, Montreal

Carl Tropper , McGill University, Montreal

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TPDS.2011.246

ABSTRACT

A major part of the design process for Integrated Circuits (IC) is the process of circuit verification, in which the correctness of a circuit's design is evaluated. Discrete event simulation is a central tool in this effort. As proscribed by Moore's law, the number of transistors which can be placed on an IC doubles every 18 months. As a result, simulation has become the major bottleneck in the circuit design process. To alleviate this difficulty, it is possible to make use of parallel (or distributed) circuit simulation. In this paper, we make use of a parallel gate-level simulator which we developed and which is based upon Time Warp. Gate-level simulations exhibit two characteristics which can easily result in either instability or severely degraded simulation performance. Because of the low computational granularity of a gate-level simulation and because the computational load varies throughout the course of the simulation, the performance of Time Warp can be either severely degraded or be unstable. Restraining the optimism of Time Warp via a bounded window and utilizing dynamic load balancing are approaches to deal with these difficulties. In this paper, we make use of learning techniques from artificial intelligence (multiagent Q-learning, simulated annealing) to develop a combined bounded window and dynamic load balancing algorithm for parallel digital logic simulation. We evaluated the performance of these algorithms on open source Sparc and Leon designs and on two Viterbi decoder designs. We observed up to 60 percent improvement in simulation time of one of the decoders using this approach.

INDEX TERMS

Parallel digital logic simulation, Verilog, dynamic load balancing, Q-learning, simulated annealing, time warp.

CITATION

Sina Meraji, Carl Tropper, "Optimizing Techniques for Parallel Digital Logic Simulation",

*IEEE Transactions on Parallel & Distributed Systems*, vol.23, no. 6, pp. 1135-1146, June 2012, doi:10.1109/TPDS.2011.246REFERENCES

- [1] E.E. Ajaltouni, A. Boukerche, and M. Zhang, "An Efficient Dynamic Load Balancing Scheme for Distributed Simulations on a Grid Infrastructure,"
DS-RT '08: Proc. 12th IEEE/ACM Int'l Symp. Distributed Simulation and Real-Time Applications, pp. 61-68, 2008.- [2] S.S. Aote and M.U. Kharat, "A Game-Theoretic Model for Dynamic Load Balancing in Distributed Systems,"
ICAC3 '09: Proc. Int'l Conf. Advances in Computing, Comm. and Control, pp. 235-238, 2009.- [3] H. Avril and C. Tropper, "Clustered Time Warp and Logic Simulation,"
SIGSIM Simulation Digest, vol. 25, no. 1, pp. 112-119, 1995.- [4] H. Avril and C. Tropper, "The Dynamic Load Balancing of Clustered Time Warp for Logic Simulation,"
SIGSIM Simulation Digest, vol. 26, no. 1, pp. 20-27, 1996.- [5] Y.-B. Lin and P.A. Fishwick, "Asynchronous Parallel Discrete Event Simulation,"
IEEE Trans. Systems, Man and Cybernetics, vol. 26, no. 4, pp. 397-412, July 1996.- [6] J.G. Carbonell,
Machine Learning: Paradigms and Methods. Elsevier North-Holland, Inc., 1990.- [7] B. Cohen,
VHDL Coding Styles and Methodologies. Kluwer Academic Publishers, 1995.- [8] S.R. Das and R.M. Fujimoto, "An Adaptive Memory Management Protocol for Time Warp Parallel Simulation,"
SIGMETRICS '94: Proc. ACM SIGMETRICS Conf. Measurement and Modeling of Computer Systems, pp. 201-210, 1994.- [9] R.M. Fujimoto,
Parallel and Distribution Simulation Systems. John Wiley and Sons, Inc., 1999.- [10] H. Gabow and R. Tarjan, "Almost-Optimum Speed-Ups of Algorithms for Bipartite Matching and Related Problems,"
STOC '88: Proc. 20th Ann. ACM Symp. Theory of Computing, pp. 514-527, 1988.- [11] D.R. Jefferson, "Virtual Time,"
ACM Trans. Programming Languages and Systems, vol. 7, no. 3, pp. 404-425, 1985.- [12] L.P. Kaelbling, M.L. Littman, and A.W. Moore, "Reinforcement Learning: A Survey,"
J. Artificial Intelligence Research, vol. 4, pp. 237-285, 1996.- [13] A.T. Kalai and S. Vempala, "Simulated Annealing for Convex Optimization,"
Math. of Operations Research, vol. 31, no. 2, pp. 253-266, 2006.- [14] S. Kirkpartick, C.D. Gelatt, and M.P. Vecchi, "Optimization by Simulated Annealing,"
Science, vol. 220, no. 4598, pp. 671-680, Jan. 1983.- [15] D.E. Knuth,
The Art of Computer Programming: Fundamental Algorithms, third ed., vol. 1. Addison Wesley Longman Publishing Co., Inc., 1997.- [16] L. Li, H. Huang, and C. Tropper, "DVS: An Object-Oriented Framework for Distributed Verilog Simulation,"
PADS '03: Proc. 17th Workshop Parallel and Distributed Simulation, pp. 173-180, 2003.- [17] T. Mason and D. Brown,
Lex & Yacc. O'Reilly and Associates, Inc., 1990.- [18] S. Meraji, W. Zhang, and C. Tropper, "A Multi-State Q-Learning Approach for the Dynamic Load Balancing of Time Warp,"
Proc. IEEE Workshop Principles of Advanced and Distributed Simulation, 2010.- [19] S. Meraji, W. Zhang, and C. Tropper, "On the Scalability and Dynamic Load-Balancing of Parallel Verilog Simulations,"
Proc. Int'l Conf. Parallel Processing (ICPP '09), 2009.- [20] G.E. Moore, "Cramming More Components onto Integrated Circuits,"
Readings in Computer Architecture, pp. 56-59, Morgan Kaufmann Publishers, Inc., 2000.- [21] MPI, Message Passing Interface, http://www-unix.mcs.anl.govmpi/, Jan. 2009.
- [22] Y. Nikulin, "Simulated Annealing Algorithm for the Robust Spanning Tree Problem,"
J. Heuristics, vol. 14, no. 4, pp. 391-402, 2008.- [23] A. Palaniswamy and P.A. Wilsey, "Adaptive Bounded Time Windows in an Optimistically Synchronized Simulator,"
Proc. Third Great Lakes Symp. VLSI, pp. 114-118, 1993.- [24] S. Palnitkar,
"Veriloghdl: A Guide to Digital Design and Synthesis," second ed. Prentice Hall Press, 2003.- [25] L. Panait and S. Luke, "Cooperative Multi-Agent Learning: The State of the Art,"
Autonomous Agents and Multi-Agent Systems, vol. 11, no. 3, pp. 387-434, 2005.- [26] S.J. Russell and P. Norvig,
Artificial Intelligence: A Modern Approach. Pearson Education, 2003.- [27] R. Schlagenhaft, M. Ruhwandl, C. Sporrer, and H. Bauer, "Dynamic Load Balancing of a Multi-Cluster Simulator on a Network of Workstations,"
SIGSIM Simulation Digest, vol. 25, no. 1, pp. 175-180, 1995.- [28] L. Sokol, D. Briscoe, and A. Wieland, "Reinforcement Learning: A Survey,"
MTW: A Strategy for Scheduling Discrete Simulation Events for Concurrent Execution, vol. 19, pp. 34-42, 1996.- [29] S. Srinivasan and P.F. ReynoldsJr., "NPSI Adaptive Synchronization Algorithms for PDES,"
Proc. Conf. Winter Simulation, pp. 658-665, 1995.- [30] X. Tong and W. Shu, "An Efficient Dynamic Load Balancing Scheme for Heterogenous Processing System,"
Proc. Int'l Conf. Computational Intelligence and Natural Computing, vol. 2, pp. 319-322, 2009.- [31] C.J.C.H. Watkins and P. Dayan, "Q-Learning,"
Machine Learning, vol. 8, nos. 3/4, pp. 279-292, 1992.- [32] A.R. Xambre and P.M. Vilarinho, "A Simulated Annealing Approach for Manufacturing Cell Formation with Multiple Identical Machines,"
European J. Operational Research, vol. 151, no. 2, pp. 434-446, 2003.- [33] Q. XU and C. Tropper, "XTW, A Parallel and Distributed Logic Simulator,"
ASP-DAC '05: Proc. Conf. Asia South Pacific Design Automation, pp. 1064-1069, 2005.- [34] B. Zhang, Z. Mo, G. Yang, and W. Zheng, "Dynamic Load Balancing Efficiently in a Large Scale Cluster,"
Int'l J. High Performance Computing and Networking, vol. 6, no. 2, pp. 100-105, 2009. |