Issue No.05 - May (2012 vol.23)
José González , Intel Corp., Intel Labs Barcelona, Barcelona
Enric Herrero , Universitat Politècnica de Catalunya, Barcelona
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TPDS.2011.200
Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the latency and high demand of the on-chip network and the off-chip memory communication. One of the main trade-offs when searching an optimal cache hierarchy is the sharing degree of cache space and its on-die distribution. Several techniques have appeared recently that optimize these parameters to get a better performance. This work provides some insight in the most promising configurations for tiled microarchitectures and shows the advantages and limitations of each of them in terms of performance and energy efficiency. This paper extends previous works by providing a complete study that evaluates different network topologies, single and multithreaded benchmarks, and single and multiprogrammed execution. In all these studies, the Distributed Cooperative Caching shows to be a promising alternative to traditional configurations for chip multiprocessors, providing a scalable and energy efficient solution.
Tiled microarchitectures, memory hierarchy, energy efficiency.
José González, Enric Herrero, "Distributed Cooperative Caching: An Energy Efficient Memory Scheme for Chip Multiprocessors", IEEE Transactions on Parallel & Distributed Systems, vol.23, no. 5, pp. 853-861, May 2012, doi:10.1109/TPDS.2011.200