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Accelerating Matrix Operations with Improved Deeply Pipelined Vector Reduction
February 2012 (vol. 23 no. 2)
pp. 202-210
ASCII Text
x 
 
Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris, "Accelerating Matrix Operations with Improved Deeply Pipelined Vector Reduction," IEEE Transactions on Parallel and Distributed Systems, vol. 23, no. 2, pp. 202-210, February, 2012.
 
 
BibTex
x
 
@article{ 10.1109/TPDS.2011.141,
author = {Yi-Gang Tai and Chia-Tien Dan Lo and Kleanthis Psarris},
title = {Accelerating Matrix Operations with Improved Deeply Pipelined Vector Reduction},
journal ={IEEE Transactions on Parallel and Distributed Systems},
volume = {23},
number = {2},
issn = {1045-9219},
year = {2012},
pages = {202-210},
doi = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2011.141},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Parallel and Distributed Systems
TI - Accelerating Matrix Operations with Improved Deeply Pipelined Vector Reduction
IS - 2
SN - 1045-9219
SP202
EP210
EPD - 202-210
A1 - Yi-Gang Tai,
A1 - Chia-Tien Dan Lo,
A1 - Kleanthis Psarris,
PY - 2012
KW - Reconfigurable hardware
KW - pipeline processors
KW - parallel algorithms
KW - parallel and vector implementations
KW - algorithm design and analysis.
VL - 23
JA - IEEE Transactions on Parallel and Distributed Systems
ER -
 
Yi-Gang Tai, University of Texas at San Antonio, San Antonio
Chia-Tien Dan Lo, Southern Polytechnic State University, Marietta
Kleanthis Psarris, University of Texas at San Antonio, San Antonio
Many scientific or engineering applications involve matrix operations, in which reduction of vectors is a common operation. If the core operator of the reduction is deeply pipelined, which is usually the case, dependencies between the input data elements cause data hazards. To tackle this problem, we propose a new reduction method with low latency and high pipeline utilization. The performance of the proposed design is evaluated for both single data set and multiple data set scenarios. Further, QR decomposition is used to demonstrate how the proposed method can accelerate its execution. We implement the design on an FPGA and compare its results to other methods.

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Index Terms:
Reconfigurable hardware, pipeline processors, parallel algorithms, parallel and vector implementations, algorithm design and analysis.
Citation:
Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris, "Accelerating Matrix Operations with Improved Deeply Pipelined Vector Reduction," IEEE Transactions on Parallel and Distributed Systems, vol. 23, no. 2, pp. 202-210, Feb. 2012, doi:10.1109/TPDS.2011.141
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