The Community for Technology Leaders
RSS Icon
Issue No.02 - February (2012 vol.23)
pp: 193-201
Fadi N. Sibai , Saudi Aramco, Dhahran
This paper introduces the Spidergon-Donut (SD) on-chip interconnection network for interconnecting 1,000 cores in future MPSoCs and CMPs. Unlike the Spidergon network, the SD network which extends the Spidergon network into the second dimension, significantly reduces the network diameter, well below the popular 2D Mesh and Torus networks for one extra node degree and roughly 25 percent more links. A detailed construction of the SD network and a method to reshuffle the SD network's nodes for layout onto the 2D plane, and simple one-to-one and broadcast routing algorithms for the SD network are presented. The various configurations of the SD network are analyzed and compared including detailed area and delay studies. To interconnect a thousand cores, the paper concludes that a hybrid version of the SD network with smaller SD instances interconnected by a crossbar is a feasible low-diameter network topology for interconnecting the cores of a thousand core system.
Many-core processors, on-chip interconnection networks, hybrid networks.
Fadi N. Sibai, "A Two-Dimensional Low-Diameter Scalable On-Chip Network for Interconnecting Thousands of Cores", IEEE Transactions on Parallel & Distributed Systems, vol.23, no. 2, pp. 193-201, February 2012, doi:10.1109/TPDS.2011.160
[1] L. Hammond, B. Nayfeh, and K. Olukotun, "A Single-Chip Multiprocessor," Computer, vol. 30, no. 9, pp. 79-85, Sept. 1997.
[2] S. Lee, S. Tam, I. Pefkianakis, S. Lu, M.F. Chang, C. Guo, G. Reinman, C. Peng, M. Naik, L. Zhang, and J. Cong, "A Scalable Micro Wireless Interconnect Structure for CMPs," Proc. MobiCom '09, pp. 217-228, 2009.
[3] V.F. Pavlidis and E.G. Friedman, "3D Topologies for Networks-on-Chip," IEEE Trans. Very Large Scale Integration Systems, vol. 15, no.10, pp. 1081-1090, Oct. 2007.
[4] A. Joshi et al., "Silicon-Photonic Clos Networks for Global on-Chip Communication," Proc. ACM/IEEE Int'l Symp. Networks-on-Chip (NOCS '09), 2009.
[5] L.P. Carloni, P. Pande, and Y. Xie, "Networks-on-Chip in Emerging Interconnect Paradigms: Advantages and Challenges," Proc. Third ACM Symp. Networks-on-Chip (NOCS '09), 2009.
[6] W. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2003.
[7] J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks: An Engineering Approach. IEEE CS Press, 1997.
[8] C. Gomez et al., "Beyond Fat-Tree: Unidirectional Load-Balanced Multistage Interconnection Network," Computer Architecture Letters, vol. 7, no. 2, pp. 49-52, 2008.
[9] M. Coppola et al., "Spidergon: A Novel on Chip Communication Network," Proc. Int'l Symp. System on Chip, 2004.
[10] L. Bononi and N. Concer, "Simulation and Analysis of Network on Chip Architectures: Ring, Spidergon and 2D Mesh," Proc. Design, Automation and Test in Europe (DATE), 2006.
[11] Multiprocessor Systems-on-Chips, A. Jerraya, W. Wolf, eds. Morgan Kaufmann, 2004.
[12] C.L. Seitz, "The Cosmic Cube," Comm. ACM, vol. 28, no. 1, pp. 22-33, 1985.
[13] F.N. Sibai, "Optimal Clustering of Hierarchical Hyper-Ring Multicomputers," J. Supercomputing, vol. 14, no. 1, pp. 53-76, 1999.
[14] F.N. Sibai, "The Hyper-Ring Network: A Cost-Efficient Topology for Scalable Multicomputers," Proc. ACM Symp. Applied Computing, pp. 607-612, 1998.
[15] L. Peh and W. Dally, "A Delay Model and Speculative Architecture of Pipe-Lined Routers," Proc. Seventh Int'l Symp. High-Performance Computer Architecture (HPCA), 2001.
[16] M. Moadeli et al., "An Analytical Performance Model for the Spidergon NoC with Virtual Channels," J. Systems Architecture, vol. 56, no. 1, pp. 16-26, 2010.
[17] J. Balfour and W.J. Dally, "Design Tradeoffs for Tiled CMP on-Chip Networks," Proc. ACM Conf. Supercomputing (ICS), 2006.
[18] S. Bourduas and Z. Zilic, "A Ring/Mesh Interconnect Using Hierarchical Rings for Global Routing," Proc. First ACM Symp. Networks-on-Chip, 2007.
[19] J. Kim, W. Dally, and D. Abts, "Flattened Butterfly: A Cost-Efficient Topology for High-Radix Networks," Proc. 34th Int'l Symp. Computer Architecture, pp. 126-137, 2007.
[20] M. Coppola, "Spidergon: A NoC for Future SMP Architectures," Proc. Fourth Forum on Application-Specific MPSoC, 2004.
[21] M. Coppola et al., Design of Cost-Efficient Interconnect Processing Units : Spidergon STNoC. CRC Press, 2008.
[22] J. Kim, "High-Radix Interconnection Networks," PhD thesis, Stanford Univ., 2008.
[23] C. Leiserson, "Fat-Trees: Universal Networks for Hardware-Efficient Supercomputing," IEEE Trans. Comp., vol. C-34, no. 10, pp. 892-901, Oct. 1985.
[24] M. Kim, J. Davis, M. Oskin, and T. Austin, "Polymorphic On-Chip Networks," Proc. 35th Int'l Symp. Computer Architecture, 2008.
[25] D. Jayasimha, B. Zafar, and Y. Hoskote, OCIN : Why They Are Different and How to Compare Them?, technical report, Intel Corporation, 2006.
[26] E. Shin, "Automated Generation of Round-Robin Arbitration and Crossbar Switch Logic," PhD dissertation, School of Electrical and Computer Eng., Georgia Institute of Tech nology, 2003.
[27] A. DeHon, "ESE680 Lecture Notes, Day 13, University of Pennsylvania, Spring 2007," lecturesDay13_6up.pdf, 2007.
[28] C. Mineo and W. Davis, "Save Your Energy : A Fast and Accurate Approach to NoC Power Estimation," Proc. 15th Int'l Symp. High-Performance Computer Architecture, 2009.
23 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool