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A Two-Dimensional Low-Diameter Scalable On-Chip Network for Interconnecting Thousands of Cores
February 2012 (vol. 23 no. 2)
pp. 193-201
Fadi N. Sibai, Saudi Aramco, Dhahran
This paper introduces the Spidergon-Donut (SD) on-chip interconnection network for interconnecting 1,000 cores in future MPSoCs and CMPs. Unlike the Spidergon network, the SD network which extends the Spidergon network into the second dimension, significantly reduces the network diameter, well below the popular 2D Mesh and Torus networks for one extra node degree and roughly 25 percent more links. A detailed construction of the SD network and a method to reshuffle the SD network's nodes for layout onto the 2D plane, and simple one-to-one and broadcast routing algorithms for the SD network are presented. The various configurations of the SD network are analyzed and compared including detailed area and delay studies. To interconnect a thousand cores, the paper concludes that a hybrid version of the SD network with smaller SD instances interconnected by a crossbar is a feasible low-diameter network topology for interconnecting the cores of a thousand core system.

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Index Terms:
Many-core processors, on-chip interconnection networks, hybrid networks.
Citation:
Fadi N. Sibai, "A Two-Dimensional Low-Diameter Scalable On-Chip Network for Interconnecting Thousands of Cores," IEEE Transactions on Parallel and Distributed Systems, vol. 23, no. 2, pp. 193-201, Feb. 2012, doi:10.1109/TPDS.2011.160
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