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Issue No.10 - Oct. (2011 vol.22)
pp: 1681-1696
Kai Ma , The Ohio State University, Columbus
Xiaorui Wang , The Ohio State University, Columbus
As chip multiprocessors (CMPs) become the main trend in processor development, various power and thermal management strategies have recently been proposed to optimize system performance while controlling the power or temperature of a CMP chip to stay below a constraint. The availability of per-core dynamic voltage and frequency scaling (DVFS) also makes it possible to develop advanced management strategies. However, most existing solutions rely on open-loop search or optimization with the assumption that power can be estimated accurately, while others adopt oversimplified feedback control strategies to control power and temperature separately, without any theoretical guarantees. In this paper, we propose a chip-level power control algorithm that is systematically designed based on optimal control theory. Our algorithm can precisely control the power of a CMP chip to the desired set point while maintaining the temperature of each core below a specified threshold. Furthermore, an online model estimator is designed to achieve analytical assurance of control accuracy and system stability, even in the face of significant workload variations or unpredictable chip or core variations. To further improve system performance, we also integrate dynamic cache resizing into our control framework so that power can be shifted among CPU cores and the shared L2 cache. Empirical results on a physical testbed show that our controller outperforms two state-of-the-art control algorithms by having better SPEC benchmark performance and more precise power control. In addition, extensive simulation results demonstrate the efficacy of our algorithm for various CMP configurations.
Power control, power capping, chip multiprocessor, cache resizing, feedback control, online model estimation.
Kai Ma, Xiaorui Wang, "Adaptive Power Control with Online Model Estimation for Chip Multiprocessors", IEEE Transactions on Parallel & Distributed Systems, vol.22, no. 10, pp. 1681-1696, Oct. 2011, doi:10.1109/TPDS.2011.39
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