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Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm
July 2011 (vol. 22 no. 7)
pp. 1142-1149
Atef Ibrahim, Electronics Research Institute, Cairo
Fayez Gebali, University of Victoria, Victoria
Hamed Elsimary, Electronics Research Institute, Cairo
Amin Nassar, Cairo University, Cairo
This paper presents a systematic methodology for exploring possible processor arrays of scalable radix 4 modular Montgomery multiplication algorithm. In this methodology, the algorithm is first expressed as a regular iterative expression, then the algorithm data dependence graph and a suitable affine scheduling function are obtained. Four possible processor arrays are obtained and analyzed in terms of speed, area, and power consumption. To reduce power consumption, we applied low power techniques for reducing the glitches and the Expected Switching Activity (ESA) of high fan-out signals in our processor array architectures. The resulting processor arrays are compared to other efficient ones in terms of area, speed, and power consumption.

[1] L. Rivest, A. Shamir, and L. Adleman, "A Method for Obtaining Digital Signatures and Public-Key Cryptosystems," Comm. ACM, vol. 21, no. 2, pp. 120-126, Feb. 1978.
[2] Nat'l Inst. for Standards and Tech nology, "Digital Signature Standard (DSS)," Fed. Information Processing Standards Publication (FIPS PUB 186-2), Jan. 2000.
[3] M. Hellman, "New Directions on Cryptography," IEEE Trans. Information Theory, vol. IT-22, no. 6, pp. 644-654, Nov. 1976.
[4] N. Koblitz, "Elliptic Curve Cryptosystems," Math. of Computation, vol. 48, no. 177, pp. 203-209, Jan. 1987.
[5] A. Menezes, Applications on Finite Fields. Kluwer Academic Publishers, 1993.
[6] B. Kaliski, Ç. Koç, and T. Acar, "Analyzing and Comparing Montgomery Multiplication Algorithms," IEEE Micro, vol. 16, no. 3, pp. 26-33, June 1996.
[7] T. Hamano, "O(n)-Depth Circuit Algorithm for Modular Exponentiation," Proc. IEEE 12th Symp. Computer Arithmetic, pp. 188-192, 1995.
[8] C. Paar and T. Blum, "Montgomery Modular Exponentiation on Reconfigurable Hardware," Proc. 14th IEEE Symp. Computer Arithmetic, pp. 70-77, 1999.
[9] J. Bajard, L. Didier, and P. Kornerup, "An RNS Montgomery Modular Multiplication Algorithm," IEEE Trans. Computers, vol. 47, no. 7, pp. 766-776, July 1998.
[10] P. Montgomery, "Modular Multiplication without Trial Division," Math. of Computation, vol. 44, no. 170, pp. 519-521, Apr. 1985.
[11] T. Yanik, E. Savas, and Ç. Koç, "Incomplete Reduction in Modular Arithmetic," Math. of Computation, vol. 149, no. 2, pp. 46-54, Mar. 2002.
[12] A. Tenca and Ç. Koç, "A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm," IEEE Trans. Computers, vol. 52, no. 9, pp. 1215-1221, Sept. 2003.
[13] A. Tenca, E. Savas, and Ç. Koç, "A Design Framework for Scalable and Unified Architectures that Perform Multiplication in gf(p) and gf($2^{m}$ )," Int'l J. Computer Research, vol. 13, no. 1, pp. 68-83, 2004.
[14] T. Todorov, A. Tenca, and Ç. Koç, "High-Radix Design of a Scalable Modular Multiplier," Cryptographic Hardware and Embedded Systems, Ç. Koç, D. Naccache, and C. Paar, ed., pp. 189-205, Springer Verlag, 2001.
[15] E. Savas, A. Tenca, M. Ciftcibasi, and Ç. Koç, "Multiplier Architectures for GF(p) and GF($2^{n}$ )," Proc. IEE Computers and Digital Techniques, vol. 151, no. 2, pp. 147-160, Mar. 2004.
[16] L. Tawalbeh and A. Tenca, "Radix-4 Asic Design of a Scalable Montgomery Modular Multiplier Using Encoding Techniques," master's thesis, Oregon State Univ., 2002.
[17] S. Rao and T. Kailath, "Regular Iterative Algorithms and Their Implementation on Processor Arrays," Proc. IEEE, vol. 76, no. 3, pp. 259-269, Mar. 1988.
[18] S. Kung, VLSI Array Processors. Prentice- Hall, 1988.
[19] E. Abdel-Raheem, "Design and Vlsi Implementation of Multirate Filter Banks," PhD dissertation, Univ. of Victoria, 1995.
[20] F. El-Guibaly and A. Tawfik, "Mapping 3D IIR Digital Filter onto Systolic Arrays," Multidimensional Systems and Signal Processing, vol. 7, no. 1, pp. 7-26, Jan. 1996.
[21] A. Refiq and F. Gebali, "Processor Array Architectures for Deep Packet Classification," IEEE Trans. Parallel and Distributed Systems, vol. 17, no. 3, pp. 241-252, Mar. 2006.
[22] H. Orup, "Simplifying Quotient Determination in High-Radix Modular Multiplication," Proc. 12th IEEE Symp. Computer Arithmetic, pp. 193-199, July 1995.
[23] G. Todorov and A. Tenca, "Asic Design, Implementation and Analysis of a Scalable High-Radix Montgomery Multiplier," master's thesis, Oregon State Univ., 2000.
[24] Ç. Koç and A. Tenca, "A Word-Based Algorithm and Architecture for Montgomery Multiplication," Cryptographic Hardware and Embedded Systems, Ç. Koç, D. Naccache, and C. Paar, ed., pp. 94-108, Springer, 1999.
[25] H. Son and S. Oh, "Design and Implementation of Scalable Low-Power Montgomery Multiplier," Proc. Int'l Conf. Computer Design, (ICCD '04), pp. 524-531, 2004.
[26] N. Pinckney and D. Harris, "Parallel High-Radix Montgomery Multipliers," Proc. 42nd Asilomar Conf. Signals, Systems and Computers, pp. 772-776, 2008.

Index Terms:
Processor array, Montgomery multiplication, scalability, cryptography, secure communications, low power modular multipliers.
Atef Ibrahim, Fayez Gebali, Hamed Elsimary, Amin Nassar, "Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm," IEEE Transactions on Parallel and Distributed Systems, vol. 22, no. 7, pp. 1142-1149, July 2011, doi:10.1109/TPDS.2010.196
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