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Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm
July 2011 (vol. 22 no. 7)
pp. 1142-1149
ASCII Text
x 
 
Atef Ibrahim, Fayez Gebali, Hamed Elsimary, Amin Nassar, "Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm," IEEE Transactions on Parallel and Distributed Systems, vol. 22, no. 7, pp. 1142-1149, July, 2011.
 
 
BibTex
x
 
@article{ 10.1109/TPDS.2010.196,
author = {Atef Ibrahim and Fayez Gebali and Hamed Elsimary and Amin Nassar},
title = {Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm},
journal ={IEEE Transactions on Parallel and Distributed Systems},
volume = {22},
number = {7},
issn = {1045-9219},
year = {2011},
pages = {1142-1149},
doi = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2010.196},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Parallel and Distributed Systems
TI - Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm
IS - 7
SN - 1045-9219
SP1142
EP1149
EPD - 1142-1149
A1 - Atef Ibrahim,
A1 - Fayez Gebali,
A1 - Hamed Elsimary,
A1 - Amin Nassar,
PY - 2011
KW - Processor array
KW - Montgomery multiplication
KW - scalability
KW - cryptography
KW - secure communications
KW - low power modular multipliers.
VL - 22
JA - IEEE Transactions on Parallel and Distributed Systems
ER -
 
Atef Ibrahim, Electronics Research Institute, Cairo
Fayez Gebali, University of Victoria, Victoria
Hamed Elsimary, Electronics Research Institute, Cairo
Amin Nassar, Cairo University, Cairo
This paper presents a systematic methodology for exploring possible processor arrays of scalable radix 4 modular Montgomery multiplication algorithm. In this methodology, the algorithm is first expressed as a regular iterative expression, then the algorithm data dependence graph and a suitable affine scheduling function are obtained. Four possible processor arrays are obtained and analyzed in terms of speed, area, and power consumption. To reduce power consumption, we applied low power techniques for reducing the glitches and the Expected Switching Activity (ESA) of high fan-out signals in our processor array architectures. The resulting processor arrays are compared to other efficient ones in terms of area, speed, and power consumption.

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Index Terms:
Processor array, Montgomery multiplication, scalability, cryptography, secure communications, low power modular multipliers.
Citation:
Atef Ibrahim, Fayez Gebali, Hamed Elsimary, Amin Nassar, "Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm," IEEE Transactions on Parallel and Distributed Systems, vol. 22, no. 7, pp. 1142-1149, July 2011, doi:10.1109/TPDS.2010.196
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