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Issue No.05 - May (2011 vol.22)
pp: 833-846
Cheng-Shang Chang , National Tsing Hua University, Hsinchu
Jay Cheng , National Tsing Hua University, Hsinchu
Duan-Shin Lee , National Tsing Hua University, Hsinchu
Chi-Feung Wu , National Tsing Hua University, Hsinchu
ABSTRACT
It is well known that output-buffered switches have better performance than other switch architectures. However, output-buffered switches also suffer from the notorious scalability problem, and direct constructions of large output-buffered switches are difficult. In this paper, we study the problem of constructing scalable switches that have comparable performance (in the sense of 100 percent throughput and first-in first-out (FIFO) delivery of packets from the same flow) to output-buffered switches. For this, we propose a new concept, called quasi-output-buffered switch. Like an output-buffered switch, a quasi-output-buffered switch is a deterministic switch that achieves 100 percent throughput and delivers packets from the same flow in the FIFO order. Using the three-stage Clos network, we show that one can recursively construct a larger quasi-output-buffered switch with a set of smaller quasi-output-buffered switches. By recursively expanding the three-stage Clos network, we obtain a quasi-output-buffered switch with only 2\times 2 switches. Such a switch is called a packet-pair switch in this paper as it always transmits packets in pairs. By computer simulations, we show that packet-pair switches have better delay performance than most load-balanced switches with comparable construction complexity.
INDEX TERMS
Delay performance, load-balanced switches, output-buffered switches, packet-pair switches, quasi-output-buffered switches.
CITATION
Cheng-Shang Chang, Jay Cheng, Duan-Shin Lee, Chi-Feung Wu, "Quasi-Output-Buffered Switches", IEEE Transactions on Parallel & Distributed Systems, vol.22, no. 5, pp. 833-846, May 2011, doi:10.1109/TPDS.2010.188
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