
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Peng Zhang, Reid Powell, Yuefan Deng, "Interlacing Bypass Rings to Torus Networks for More Efficient Networks," IEEE Transactions on Parallel and Distributed Systems, vol. 22, no. 2, pp. 287295, February, 2011.  
BibTex  x  
@article{ 10.1109/TPDS.2010.89, author = {Peng Zhang and Reid Powell and Yuefan Deng}, title = {Interlacing Bypass Rings to Torus Networks for More Efficient Networks}, journal ={IEEE Transactions on Parallel and Distributed Systems}, volume = {22}, number = {2}, issn = {10459219}, year = {2011}, pages = {287295}, doi = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2010.89}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Parallel and Distributed Systems TI  Interlacing Bypass Rings to Torus Networks for More Efficient Networks IS  2 SN  10459219 SP287 EP295 EPD  287295 A1  Peng Zhang, A1  Reid Powell, A1  Yuefan Deng, PY  2011 KW  Network topology KW  torus networks KW  bypass ring KW  network diameter KW  nodetonode distance KW  routing. VL  22 JA  IEEE Transactions on Parallel and Distributed Systems ER   
[1] N.R. Adiga et al., "An Overview of the BlueGene/L Supercomputer," Proc. IEEE/ACM Supercomputing Conf., 2002.
[2] M.A. Blumrich et al., "Design and Analysis of the BlueGene/L Torus Interconnection Network," IBM Research Report, 2003.
[3] S.L. Scott and G.M. Thorson, "The Cray T3E Network: Adaptive Routing in a High Performance 3D Torus," Proc. Symp. High Performance Interconnects (Hot Interconnects 4), pp. 157160, 1996.
[4] E. Anderson et al., "Performance of the CRAY T3E Multiprocessor," Proc. ACM/IEEE Conf. Supercomputing, CDROM, 1997.
[5] TOP500. Top 500 Supercomputer Sites, http:/www.top500.org, 2010.
[6] K.J. Barker et al., "Entering the Petaflop Era: The Architecture and Performance of Roadrunner," Proc. ACM/IEEE Conf. Supercomputing, 2008.
[7] L.N. Bhuyan and D.P. Agrawal, "Generalized Hypercube and Hyperbus Structures for a Computer Network," IEEE Trans. Computers, vol. C33, no. 4, pp. 323333, Apr. 1984.
[8] F. Harary, J.P. Hayes, and H.J. Wu, "A Survey of the Theory of Hypercube Graphs," Computers and Math. with Applications, vol. 15, no. 4, pp. 277289, 1988.
[9] K. Efe, "A Variation on the Hypercube with Lower Diameter," IEEE Trans. Computers, vol. 40, no. 11, pp. 13121316, Nov. 1991.
[10] R.P. Kaushal and J.S. Bedi, "Comparison of Hypercube, Hypernet, and Symmetric Hypernet Architectures," ACM SIGARCH Computer Architecture News, vol. 20, no. 5, pp. 1325, 1992.
[11] V. Heun and E.W. Mayr, "Efficient Embeddings into HypercubeLike Topologies," The Computer J., vol. 46, no. 6, pp. 632644, 2003.
[12] F.P. Preparata and J. Vuillemin, "The CubeConnected Cycles: A Versatile Network for Parallel Computation," Comm. ACM, vol. 24, no. 5, pp. 300309, 1981.
[13] A. Harwood and H. Shen, "A Low Cost Hybrid FatTree Interconnection Network," Proc. Int'l Conf. Parallel and Distributed Processing and Applications, 1998.
[14] B. Parhami and D.M. Kwai, "Incomplete kary nCube and Its Derivatives," J. Parallel and Distributed Computing, vol. 64, no. 2, pp. 183190, 2004.
[15] I. Stojmenovic, "Honeycomb Networks: Topological Properties and Communication Algorithms," IEEE Trans. Parallel and Distributed Systems, vol. 8, no. 10, pp. 10361042, Oct. 1997.
[16] C. Decayeux and D. Seme, "3D Hexagonal Network: Modeling, Topological Properties, Addressing Scheme and Optimal Routing Algorithm," IEEE Trans. Parallel and Distributed Systems, vol. 16, no. 9, pp. 875884, Sept. 2005.
[17] W.W. Kirkman and D. Quammen, "Packed Exponential Connections—a Hierarchy of 2D Meshes," Proc. Fifth Int'l. Parallel Processing Symp., 1991.
[18] Y. Inoguchi and S. Horiguchi, "Shifted Recursive Torus Interconnection for High Performance Computing," Proc. IEEE CS HighPerformance Computing on the Information Superhighway (HPCAsia '97), 1997.
[19] V.K. Jain and S. Horiguchi, "VLSI Considerations for TESH: A New Hierarchical Interconnection Network for 3D Integration," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 6, no. 3, pp. 346353, Sept. 1998.
[20] Y. Yang et al., "Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers," IEEE Trans. Parallel and Distributed Systems, vol. 12, no. 7, pp. 701715, July 2001.
[21] W.J. Dally, "Performance Analysis of kary nCube Interconnection Networks," IEEE Trans. Computers, vol. 39, no. 6, pp. 775785, June 1990.
[22] J. Duato, S. Yalamanchili, and N. Lionel, Interconnection Networks: An Engineering Approach. Morgan Kaufmann Publishers Inc., 2002.
[23] W. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., 2003.
[24] B. Parhami, "Swapped Interconnection Networks: Topological, Performance, and Robustness Attributes," J. Parallel and Distributed Computing, vol. 65, no. 11, pp. 14431452, 2005.
[25] N. Chaki et al., "A New Logical Topology Based on Barrel Shifter Network over an All Optical Network," Proc. 28th Ann. IEEE CS Int'l Conf. Local Computer Networks, 2003.
[26] M.R. Samatham and D.K. Pradhan, "The de Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI," IEEE Trans. Computers, vol. 38, no. 4, pp. 567581, Apr. 1989.