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Automatic Prefetch and Modulo Scheduling Transformations for the Cell BE Architecture
April 2010 (vol. 21 no. 4)
pp. 494-505
Nikola Vujic, Barcelona Supercomputing Center, Barcelona
Marc Gonzàlez, Technical University of Catalonia, Barcelona
Xavier Martorell, Barcelona Supercomputing Center, Barcelona
Eduard Ayguadé, Barcelona Supercomputing Center, Barcelona
Ease of programming is one of the main requirements for the broad acceptance of multicore systems without hardware support for transparent data transfer between local and global memories. Software cache is a robust approach to provide the user with a transparent view of the memory architecture; but this software approach can suffer from poor performance. In this paper, we propose a hierarchical, hybrid software-cache architecture that targets enabling prefetch techniques. Memory accesses are classified at compile time into two classes: high locality and irregular. Our approach then steers the memory references toward one of two specific cache structures optimized for their respective access pattern. The specific cache structures are optimized to enable high-level compiler optimizations to aggressively unroll loops, reorder cache references, and/or transform surrounding loops so as to practically eliminate the software-cache overhead in the innermost loop. The cache design enables automatic prefetch and modulo scheduling transformations. Performance evaluation indicates that optimized software-cache structures combined with the proposed prefetch techniques translate into speedup between 10 and 20 percent. As a result of the proposed technique, we can achieve similar performance on the Cell BE processor as on a modern server-class multicore such as the IBM PowerPC 970MP processor for a set of parallel NAS applications.

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Index Terms:
Multicore processor, local memories, software cache, prefetch code generation.
Nikola Vujic, Marc Gonzàlez, Xavier Martorell, Eduard Ayguadé, "Automatic Prefetch and Modulo Scheduling Transformations for the Cell BE Architecture," IEEE Transactions on Parallel and Distributed Systems, vol. 21, no. 4, pp. 494-505, April 2010, doi:10.1109/TPDS.2009.97
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