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Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming
August 2009 (vol. 20 no. 8)
pp. 1142-1157
ASCII Text
x 
 
Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Jing Du, Ying Zhang, "Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming," IEEE Transactions on Parallel and Distributed Systems, vol. 20, no. 8, pp. 1142-1157, August, 2009.
 
 
BibTex
x
 
@article{ 10.1109/TPDS.2008.170,
author = {Xuejun Yang and Xiaobo Yan and Zuocheng Xing and Yu Deng and Jiang Jiang and Jing Du and Ying Zhang},
title = {Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming},
journal ={IEEE Transactions on Parallel and Distributed Systems},
volume = {20},
number = {8},
issn = {1045-9219},
year = {2009},
pages = {1142-1157},
doi = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2008.170},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Parallel and Distributed Systems
TI - Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming
IS - 8
SN - 1045-9219
SP1142
EP1157
EPD - 1142-1157
A1 - Xuejun Yang,
A1 - Xiaobo Yan,
A1 - Zuocheng Xing,
A1 - Yu Deng,
A1 - Jiang Jiang,
A1 - Jing Du,
A1 - Ying Zhang,
PY - 2009
KW - Microprocessors
KW - computer languages
KW - compilers
KW - programming.
VL - 20
JA - IEEE Transactions on Parallel and Distributed Systems
ER -
 
Xuejun Yang, National University of Defense Technology, Changsha
Xiaobo Yan, National University of Defense Technology, Changsha
Zuocheng Xing, National University of Defense Technology, Changsha
Yu Deng, National University of Defense Technology, Changsha
Jiang Jiang, National University of Defense Technology, Changsha
Jing Du, National University of Defense Technology, Changsha
Ying Zhang, National University of Defense Technology, Changsha
The stream architecture is a novel microprocessor architecture with wide application potential. It is critical to study how to use the stream architecture to accelerate scientific computing programs. However, existing stream processors and stream programming languages are not designed for scientific computing. To address this issue, we design and implement a 64-bit stream processor, Fei Teng 64 (FT64), which has a peak performance of 16 Gflops. FT64 supports two kinds of communications, message passing and stream communications, based on which, an interconnection architecture is designed for a FT64-based high-performance computer. This high-performance computer contains multiple modules, with each module containing eight FT64s. We also design a novel stream programming language, Stream Fortran 95 (SF95), together with the compiler SF95Compiler, so as to facilitate the development of scientific applications. We test nine typical scientific application kernels on our FT64 platform to evaluate this design. The results demonstrate the effectiveness and efficiency of FT64 and its compiler for scientific computing.

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Index Terms:
Microprocessors, computer languages, compilers, programming.
Citation:
Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Jing Du, Ying Zhang, "Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming," IEEE Transactions on Parallel and Distributed Systems, vol. 20, no. 8, pp. 1142-1157, Aug. 2009, doi:10.1109/TPDS.2008.170
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