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Issue No.05 - May (2009 vol.20)
pp: 710-724
Mounir Hamdi , Hong Kong University of Science and Technology, Hong Kong
Feng Wang , Hong Kong University of Science and Technology, Hong Kong
ABSTRACT
This paper addresses the design of high-performance buffers for high-end Internet routers. The buffers are typically implemented using a combination of SRAM and DRAM technologies in order to simultaneously meet the routers' high speed and capacity requirements. The major challenge in designing router buffers is to maintain multiple flow queues in the memory, unlike computer memory buffers (i.e., memory system). The major objective is to minimize the use of expensive but fast SRAM while providing acceptable delay guarantees to packets. In this paper, we first investigate hybrid SRAM/DRAM solutions proposed in the past. We show that one of the architectural limitations of these solutions is that the required SRAM size grows linearly with the number of flows in the system. This prevents the solutions from scaling to support a large number of flows. We then break down this shortcoming by proposing a parallel hybrid SRAM/DRAM (PHSD) architecture. We design a series of memory management algorithms (MMAs) for PHSD, based on tradeoffs between the complexity of the MMAs and the guarantee of in-order delivery of packets (segmentations). We perform a detailed analysis of the proposed algorithms and conduct extensive simulations to show that PHSD can significantly outperform solutions proposed in the past in terms of the SRAM requirements and packet delay.
INDEX TERMS
Router memory, SRAM/DRAM, packet scheduling.
CITATION
Mounir Hamdi, Feng Wang, "Using Parallel DRAM to Scale Router Buffers", IEEE Transactions on Parallel & Distributed Systems, vol.20, no. 5, pp. 710-724, May 2009, doi:10.1109/TPDS.2008.162
REFERENCES
[1] J. Garcia, J. Corbal, L. Cerda, and M. Valero, “Design and Implementation of High-Performance Memory Systems for Future Packet Buffers,” Proc. 36th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO-36 '03), pp. 372-384, 2003.
[2] Y. Ganjali and N. McKeown, “Update on Buffer Sizing in Internet Routers,” ACM SIGCOMM Computer Comm. Rev., vol. 36, no. 5, pp. 67-70, 2006.
[3] J. Garcia-Vidal, M. March, L. Cerda, J. Corbal, and M. Valero, “A DRAM/SRAM Memory Scheme for Fast Packet Buffers,” IEEE Trans. Computers, vol. 55, no. 5, pp. 588-602, May 2006.
[4] J. Garcia, M. March, L. Cerda, J. Corbal, and M. Valero, “On the Design of Hybrid DRAM/SRAM Memory Schemes for Fast Packet Buffers,” Proc. Workshop High Performance Switching and Routing (HPSR '04), pp. 15-19, 2004.
[5] S. Iyer, R. Kompella, and N. McKeowa, “Analysis of a Memory Architecture for Fast Packet Buffers,” Proc. IEEE Workshop High Performance Switching and Routing (HPSR '01), pp. 368-373, 2001.
[6] J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 2003.
[7] Y. Tamir and G. Frazier, “High-Performance Multi-Queue Buffers for VLSI Communications Switches,” ACM SIGARCH Computer Architecture News, vol. 16, no. 2, pp. 343-354, 1988.
[8] A. Demers, S. Keshavt, and S. Shenker, “Analysis and Simulation of a Fair Queueing Algorithm,” Proc. ACM SIGCOMM '89, pp. 3-12, 1989.
[9] S. Iyer, R. Kompella, and N. McKeown, “Designing Buffers for Router Line Cards,” Technical Report TR02-HPNG-031001, Stanford Univ., Nov. 2002.
[10] C. Chang, D. Lee, Y. Shih, and C. Yu, “Mailbox Switch: A Scalable Two-Stage Switch Architecture for Conflict Resolution of Ordered Packets,” IEEE Trans. Comm., vol. 56, no. 1, pp. 136-149, 2008.
[11] I. Keslassy and N. McKeown, “Maintaining Packet Order in Two-Stage Switches,” Proc. IEEE INFOCOM '02, vol. 2, 2002.
[12] N. McKeown, “The iSLIP Scheduling Algorithm for Input-Queued Switches,” IEEE/ACM Trans. Networking, vol. 7, no. 2, pp. 188-201, 1999.
[13] D. Serpanos and P. Antoniadis, “FIRM: A Class of Distributed Scheduling Algorithms for High-Speed ATM Switches with Multiple Input Queues,” Proc. IEEE INFOCOM '00, vol. 2, 2000.
[14] H. Chao and J. Park, “Centralized Contention Resolution Schemes for a Large-Capacity Optical ATM Switch,” Proc. IEEE ATM Workshop, pp. 11-16, 1998.
[15] S. Chuang, A. Goel, N. McKeown, and B. Prabhakar, “Matching Output Queueing with a Combined Input/Output-Queued Switch,” IEEE J. Selected Areas in Comm., vol. 17, no. 6, pp. 1030-1039, 1999.