Issue No.03 - March (2009 vol.20)
Rama Sangireddy , University of Texas at Dallas, Richardson
Hui Wang , University of Texas at Dallas, Richardson
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TPDS.2008.97
The resource sharing nature of Simultaneous Multithreading (SMT) processors and the presence of long latency instructions from concurrent threads make the instruction scheduling window (IW), which is a primary shared component among key pipeline structures in SMT, a performance bottleneck. Due to the tight constraints on its physical size, the IW faces more severe pressure to handle the instructions from various threads while attempting to avoid resource monopolization by some low-ILP threads. It is particularly challenging to optimize the efficiency and fairness in IW utilization to fulfill the affordable performance by SMT under the shadow of long latency instructions. Most of the existing optimization schemes in SMT processors rely on the fetch policy to control the instructions that are allowed to enter the pipeline, while little effort is put to control the long latency instructions that are already located in the IW. In this paper, we propose streamline buffers to handle the long latency instructions that have already entered the pipeline and clog the IW, while the controlling fetch policies take time to react. Each streamline buffer extracts from IW and holds a chain of instructions from a thread that are stalled by dependency on a long latency load.
Multithreaded processors, Speculative multi-threading, Support for multi-threaded execution
Rama Sangireddy, Hui Wang, "Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors", IEEE Transactions on Parallel & Distributed Systems, vol.20, no. 3, pp. 389-403, March 2009, doi:10.1109/TPDS.2008.97