This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination
January 2009 (vol. 20 no. 1)
pp. 13-24
Alejandro Martínez, Universitat Politècnica de Catalunya, Barcelona
Pedro J. García, University of Castilla-La Mancha, Albacete
Francisco J. Alfaro, University of Castilla-La Mancha, Albacete
José L. Sánchez, University of Castilla-La Mancha, Albacete
José Flich, Technical University of Valencia, Valencia
Francisco J. Quiles, University of Castilla-La Mancha, Albacete
José Duato, Technical University of Valencia, Valencia
Both QoS support and congestion management techniques become essential to achieve good network performance in current high-speed interconnection networks. The most effective techniques traditionally considered for both issues, however, require too many resources for being implemented. In this paper we propose a new cost-effective switch architecture able to face the challenges of congestion management and, at the same time, to provide QoS. The efficiency of our proposal is based on using the resources (queues) used by RECN (an efficient Head-Of-Line blocking elimination technique) also for QoS support, without increasing queue requirements. Provided results show that the new switch architecture is able to guarantee QoS levels without any degradation due to congestion situations.

[1] M.J. Karol, M.G. Hluchyj, and S.P. Morgan, “Input versus Output Queueing on a Space-Division Packet Switch,” IEEE Trans. Comm., vol. 35, pp. 1347-1356, 1987.
[1] E. Anderson, J. Brooks, C. Grassl, and S. Scott, “Performance of the Cray T3E Multiprocessor,” Proc. ACM/IEEE Conf. Supercomputing (SC '97), pp. 1-17, 1997.
[2] InfiniBand Architecture Specification Volume 1, Release 1.0, InfiniBand Trade Assoc., Oct. 2000.
[2] W.C. Athas and C.L. Seitz, “Multicomputers: Message-Passing Concurrent Computers,” Computer, vol. 21, pp. 9-24, 1988.
[3] QsNet Overview, white paper, Quadrics Ltd., http:/www. quadrics.com, 2005.
[3] Y.A. Ashir and I.A. Stewart, “On Embedding Cycles in $k$ -ary $n$ -cubes,” Parallel Processing Letters, vol. 7, pp. 49-55, 1997.
[4] Myrinet, Myricom Inc., http:/www.myrinet.com, 2005.
[4] S. Bettayeb, “On the $k$ -ary Hypercube,” Theoretical Computer Science, vol. 140, pp. 333-339, 1995.
[5] W.J. Dally, P. Carvey, and L. Dennison, “Architecture of the Avici Terabit Switch/Router,” Proc. Sixth Symp. High-Performance Interconnects (Hot Interconnects '98), pp. 41-50, 1998.
[5] S. Borkar, R. Cohen, G. Cox, S. Gleason, T. Gross, H.T. Kung, M. Lam, B. Moore, C. Peterson, J. Pieper, L. Rankin, P.S. Tseng, J. Sutton, J. Urbanski, and J. Webb, “iWarp: An Integrated Solution to High-Speed Parallel Computing,” Proc. ACM/IEEE Conf. Supercomputing (SC '88), pp. 330-339, 1988.
[6] T. Anderson, S. Owicki, J. Saxe, and C. Thacker, “High-Speed Switch Scheduling for Local-Area Networks,” ACM Trans. Computer Systems, vol. 11, no. 4, pp. 319-352, Nov. 1993.
[6] B. Bose, B. Broeg, Y. Kwon, and Y. Ashir, “Lee Distance and Topological Properties of $k$ -ary $n$ -cubes,” IEEE Trans. Computers, vol. 44, pp. 1021-1030, 1995.
[7] P.J. García, J. Flich, J. Duato, I. Johnson, F.J. Quiles, and F. Naven, “Efficient, Scalable Congestion Management for Interconnection Networks,” IEEE Micro, vol. 26, no. 5, pp. 52-66, Sept. 2006.
[7] Y. Bruck, R. Cypher, and C.T. Ho, “Efficient Fault-Tolerant Mesh and Hypercube Architectures,” Proc. 22nd Int'l Symp. Fault-Tolerant Computing (FTCS '92), pp. 162-169, 1992.
[8] J. Duato, S. Yalamanchili, M.B. Caminero, D. Love, and F.J. Quiles, “MMR: A High-Performance Multimedia Router. Architecture and Design Trade-Offs,” Proc. 11th Symp. High Performance Computer Architecture (HPCA '99), Jan. 1999.
[8] J.P. Brunet and S.L. Johnsson, “All-to-All Broadcast and Applications on the Connection Machine,” Int'l J. Supercomputer Applications, vol. 6, pp. 241-256, 1992.
[9] Advanced Switching Core Architecture Specification, Revision 1.1, Advanced Switching Interconnect Special Interest Group, Mar. 2005.
[9] J.M. Chang, J.S. Yang, J.S. Yang, Y.L. Wang, and Y. Cheng, “Panconnectivity, Fault-Tolerant Hamiltonicity and Hamiltonian-Connectivity in Alternating Group Graphs,” Networks, vol. 44, pp.302-310, 2004.
[10] A. Martínez, F.J. Alfaro, J.L. Sánchez, and J. Duato, “Providing Full QoS Support in Clusters Using Only Two VCs at the Switches,” Proc. 12th Int'l Conf. High Performance Computing (HiPC '05), pp. 158-169, http://investigacion.uclm.es/portali/documentos it_1131561750-HiPC05.pdf, Dec. 2005.
[10] R. Duncan, “A Survey of Parallel Computer Architectures,” Computer, vol. 23, pp. 5-16, 1990.
[11] A. Martínez, P.J. García, F.J. Alfaro, J. Flich, J.L. Sánchez, F.J. Quiles, and J. Duato, “A Cost-Effective Interconnection Architecture with QoS and Congestion Management Support,” Proc. European Conf. Parallel Computing (EuroPar '06), Aug. 2006.
[11] T.H. Duncan, “Performance of the Intel iPSC/860 and Ncube 6400 Hypercubes,” Parallel Computing, vol. 17, pp. 1285-1302, 1991.
[12] J. Duato, S. Yalamanchili, and N. Lionel, Interconnection Networks: An Engineering Approach. Morgan Kaufmann, 2002.
[12] J. Fan, X. Lin, and X. Jia, “Node-Pancyclicity and Edge-Pancyclicity of Crossed Cubes,” Information Processing Letters, vol. 93, pp. 133-138, 2005.
[13] W.J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2003.
[13] J.F. Fang, “The Bipanconnectivity and m-Panconnectivity of the Folded Hypercube,” Theoretical Computer Science, vol. 385, pp. 286-300, 2007.
[14] M.A. Marsan, A. Bianco, P. Giaccone, E. Leonardi, and F. Neri, “Packet-Mode Scheduling in Input-Queued Cell-Based Switches,” IEEE/ACM Trans. Networking, vol. 10, no. 5, pp. 666-678, 2002.
[14] S.Y. Hsieh and G.H. Chen, “Pancyclicity of Möbius Cubes with Maximal Edge Faults,” Parallel Computing, vol. 30, pp. 407-421, 2004.
[15] P. Shivakumar and N.P. Jouppi, “CACTI 3.0: An Integrated Cache Timing, Power, and Area Model,” technical report, Compaq Western Research Laboratory, 2001.
[15] S.Y. Hsieh, T.J. Lin, and H.L. Huang, “Panconnectivity and Edge-Pancyclicity of 3-Ary $n$ -cubes,” J. Supercomputing, vol. 42, pp. 225-233, 2007.
[16] I. Elhanany, D. Chiou, V. Tabatabaee, R. Noro, and A. Poursepanj, “The Network Processing Forum Switch Fabric Benchmark Specifications: An Overview,” IEEE Network, pp. 5-9, Mar. 2005.
[16] R.E. Kessler and J.L. Schwarzmeier, “CRAY T3D: A New Dimension for Cray Research,” Proc. 38th IEEE Int'l Computer Conf. (COMPCON '93), pp. 176-182, 1993.
[17] J. Duato, I. Johnson, J. Flich, F. Naven, P.J. García, and T. Nachiondo, “A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks,” Proc. 11th Symp. High Performance Computer Architecture (HPCA), 2005.
[17] Y. Kikuchi and T. Araki, “Edge-Bipancyclicity and Edge-Fault-Tolerant Bipancyclicity of Bubble-Sort Graphs,” Information Processing Letters, vol. 100, pp. 52-59, 2006.
[18] P.J. García, J. Flich, J. Duato, I. Johnson, F.J. Quiles, and F. Naven, “Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture,” Proc. Int'l Conf. High Performance Embedded Architectures and Compilers (HiPEAC '05), pp. 266-285, Nov. 2005.
[18] F.T. Leighton, Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes. Morgan Kaufmann, 1992.
[19] Generic Coding of Moving Pictures and Associated Audio, Moving Picture Experts Group, Rec. H.262., Draft Int'l Standard ISO/IEC 13818-2, 1994.
[19] T.K. Li, C.H. Tsai, J.J.M. Tan, and L.H. Hsu, “Bipanconnectivity and Edge-Fault-Tolerant Bipancyclicity of Hypercubes,” Information Processing Letters, vol. 87, pp. 107-110, 2003.
[20] M. Ma, G. Liu, and J.M. Xu, “Panconnectivity and Edge-Fault-Tolerant Pancyclicity of Augmented Cubes,” Parallel Computing, vol. 33, pp. 36-42, 2007.
[21] M.D. Noakes, D.A. Wallach, and W.J. Dally, “The J-Machine Multicomputer: An Architectural Evaluation,” Proc. 20th Ann. Int'l Symp. Computer Architecture (ISCA '93), pp. 224-235, 1993.
[22] J.H. Park, H.C. Kim, and H.S. Lim, “Panconnectivity and Pancyclicity of Hypercube-Like Interconnection Networks with Faulty Elements,” Theoretical Computer Science, vol. 377, pp.170-180, 2007.
[23] C.L. Seitz, “The Cosmic Cube,” Comm. ACM, vol. 28, pp. 22-33, 1985.
[24] C.L. Seitz, W.C. Athas, C.M. Flaig, A.J. Martin, J. Scizovic, C.S. Steele, and W.-K. Su, “Submicron Systems Architecture Project Semiannual Technical Report,” Technical Report Caltec-CS-TR-88-18, California Inst. of Tech nology, 1988.
[25] C.H. Tsai, “Linear Array and Ring Embeddings in Conditional Faulty Hypercubes,” Theoretical Computer Science, vol. 314, pp.431-443, 2004.
[26] C.H. Tsai and S.Y. Jang, “Path Bipancyclicity of Hypercubes,” Information Processing Letters, vol. 101, pp. 93-97, 2007.
[27] D. Wang, T. An, M. Pan, K. Wang, and S. Qu, “Hamiltonian-Like Properties of $k$ -ary $n$ -cubes,” Proc. Sixth Int'l Conf. Parallel and Distributed Computing, Applications and Technologies (PDCAT '05), pp. 1002-1007, 2005.
[28] J.M. Xu, Z.Z. Du, and M. Xu, “Edge-Fault-Tolerant Edge-Bipancyclicity of Hypercubes,” Information Processing Letters, vol. 96, pp. 146-150, 2005.
[29] M. Xu, X.D. Hu, and Q. Zhu, “Edge-Bipancyclicity of Star Graphs under Edge-Fault Tolerant,” Applied Math. and Computation, vol. 183, pp. 972-979, 2006.
[30] J.M. Xu and M.J. Ma, “Cycles in Folded Hypercubes,” Applied Math. Letters, vol. 19, pp. 140-145, 2006.
[31] M.C. Yang, T.K. Li, J.J.M. Tan, and L.H. Hsu, “Fault-Tolerant Cycle-Embedding of Crossed Cubes,” Information Processing Letters, vol. 88, pp. 149-154, 2003.

Index Terms:
Interconnection architectures, Parallel Architectures
Citation:
Alejandro Martínez, Pedro J. García, Francisco J. Alfaro, José L. Sánchez, José Flich, Francisco J. Quiles, José Duato, "A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination," IEEE Transactions on Parallel and Distributed Systems, vol. 20, no. 1, pp. 13-24, Jan. 2009, doi:10.1109/TPDS.2008.62
Usage of this product signifies your acceptance of the Terms of Use.