The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.08 - August (2008 vol.19)
pp: 1111-1123
ABSTRACT
Advanced Switching (AS) is a network technology that expands the capabilities of PCI-Express adding new features like peer-to-peer communication. Together, PCI Express and AS have the potential for building the next generation interconnects. Furthermore, the provision of Quality of Service (QoS) in computing and communication environments is currently the focus of much discussion and research in industry and academia. In this paper we propose a framework to provide QoS based on bandwidth, latency, and jitter over AS employing the mechanisms provided by AS. We also present several implementations for the output scheduling mechanism. Finally, we evaluate our proposals by simulation, comparing the performance of the schedulers that we propose and their implementation complexity.
INDEX TERMS
Network Architecture and Design, Packet-switching networks, High-speed, Performance of Systems
CITATION
Raúl Martínez, Francisco J. Alfaro, José L. Sánchez, "A Framework to Provide Quality of Service over Advanced Switching", IEEE Transactions on Parallel & Distributed Systems, vol.19, no. 8, pp. 1111-1123, August 2008, doi:10.1109/TPDS.2007.70799
REFERENCES
[1] Advanced Switching Interconnect Special Interest Group, Advanced Switching Core Architecture Specification. Revision 1.1, Mar. 2005.
[2] F.J. Alfaro, J.L. Sánchez, and J. Duato, “A New Proposal to Fill in the InfiniBand Arbitration Tables,” Proc. 32nd IEEE Int'l Conf. Parallel Processing (ICPP '03), pp. 133-140, Oct. 2003.
[3] F.J. Alfaro, J.L. Sánchez, and J. Duato, “QoS in InfiniBand Subnetworks,” IEEE Trans. Parallel and Distributed Systems, vol. 15, no. 9, pp. 810-823, Sept. 2004.
[4] T. Anderson, S. Owicki, J. Saxe, and C. Thacker, “High-Speed Switch Scheduling for Local-Area Networks,” ACM Trans. Computer Systems, vol. 11, no. 4, pp. 319-352, Nov. 1993.
[5] L. Cheng, N. Muralimanohar, K. Ramani, R. Balasubramonian, and J.B. Carter, “Interconnect-Aware Coherence Protocols for Chip Multiprocessors,” Proc. 33rd Int'l Symp. Computer Architecture (ISCA '06), pp. 339-351, 2006.
[6] N. Chrysos and M. Katevenis, “Multiple Priorities in a Two-Lane Buffered Crossbar,” Proc. IEEE Global Telecomm. Conf. (Globecom '04), Nov. 2004.
[7] A. Demers, S. Keshav, and S. Shenker, “Analysis and Simulations of a Fair Queuing Algorithm,” Proc. ACM SIGCOMM, 1989.
[8] J. Duato, S. Yalamanchili, and N. Lionel, Interconnection Networks. An Engineering Approach. Morgan Kaufmann, 2002.
[9] M.A. El-Gendy, A. Bose, and K.G. Shin, “Evolution of the Internet QoS and Support for Soft Real-Time Applications,” Proc. IEEE, vol. 91, no. 7, pp. 1086-1104, 2003.
[10] S.J. Golestani, “A Self-Clocked Fair Queueing Scheme for Broadband Applications,” Proc. IEEE INFOCOM, 1994.
[11] G. Horn and T. Sdring, “SH: A Simple Distributed Bandwidth Broker for Source-Routed Loss-Less Networks,” Proc. IASTED Int'l Conf. Computer, Networks and Information Security, 2005.
[12] 802.1D-2004: Standard for Local and Metropolitan Area Networks, IEEE, http://grouper.ieee.org/groups/8021/, 2004.
[13] R. Jain, The Art of Computer System Performance Analysis: Techniques for Experimental Design, Measurement, Simulation and Modeling. JohnWiley & Sons, 1991.
[14] S.S. Kanhere, H. Sethu, and A.B. Parekh, “Fair and Efficient Packet Scheduling Using Elastic Round Robin,” IEEE Trans. Parallel and Distributed Systems, 2002.
[15] M. Katevenis, G. Passas, D. Simos, I. Papaefstathiou, and N. Chrysos, “Variable Packet Size Buffered Crossbar (CICQ) Switches,” Proc. IEEE Int'l Conf. Comm. (ICC '04), pp. 20-24, June 2004.
[16] M. Katevenis, S. Sidiropoulos, and C. Courcoubetis, “Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip,” IEEE J. Selected Areas in Comm., Oct. 1991.
[17] P. Krishna, N. Patel, A. Charny, and R. Simcoe, “On the Speedup Required for Work-Conserving Crossbar Switches,” IEEE J.Selected Areas in Comm., vol. 17, no. 6, pp. 1057-1066, June 1999.
[18] R. Martínez, F.J. Alfaro, and J.L. Sánchez, “Decoupling the Bandwidth and Latency Bounding for Table-Based Schedulers,” Proc. 35th IEEE Int'l Conf. Parallel Processing (ICPP '06), Aug. 2006.
[19] R. Martínez, F.J. Alfaro, and J.L. Sánchez, “Evaluating Several Implementations for the AS Minimum Bandwidth Egress Link Scheduler,” Proc. 15th Int'l Conf. Computer Comm. and Networks (ICCCN '06), Oct. 2006.
[20] R. Martínez, F.J. Alfaro, and J.L. Sánchez, “Implementing the Advanced Switching Minimum Bandwidth Egress Link Scheduler,” Proc. Fifth IEEE Int'l Symp. Network Computing and Applications (NCA '06), July 2006.
[21] R. Martínez, F.J. Alfaro, and J.L. Sánchez, “Providing Quality of Service over Advanced Switching,” Proc. 12th Int'l Conf. Parallel and Distributed Systems (ICPADS '06), July 2006.
[22] R. Martínez, F.J. Alfaro, J.L. Sánchez, and T. Skeie, “A First Approach to Provide QoS in Advanced Switching,” Proc. 12th Int'l Conf. High Performance Computing (HiPC), 2005.
[23] D. Mayhew and V. Krishnan, “PCI Express and Advanced Switching: Evolutionary Path to Building Next Generation Interconnects,” Proc. 11th Symp. High Performance Interconnects—Hot Interconnects (HOT-I), 2003.
[24] P.L. Montessoro and D. Pierattoni, “Advanced Research Issues for Tomorrow's Multimedia Networks,” Proc. Int'l Symp. Information Technology (ITCC), 2001.
[25] A.K. Parekh and R.G. Gallagher, “A Generalized Processor Sharing Approach to Flow Control in Integrated Services Networks: The Multiple Node Case,” IEEE/ACM Trans. Networking, 1994.
[26] K.I. Park, QoS in Packet Networks. Springer, 2005.
[27] PCI SIG, PCI Express Base Architecture Specification. Revision 1.0a, Apr. 2003.
[28] J. Pelissier, “Providing Quality of Service over Infiniband Architecture Fabrics,” Proc. Eighth Symp. High Performance Interconnects—Hot Interconnects (HOT-I '00), Aug. 2000.
[29] G. Pfister and A. Norton, “Hot Spot Contention and Combining in Multistage Interconnection Networks,” IEEE Trans. Computers, vol. 34, no. 10, pp. 943-948, Oct. 1985.
[30] S.A. Reinemo, F.O. Sem-Jacobsen, T. Skeie, and O. Lysne, “Admission Control for Diffserv Based Quality of Service in Cut-Through Networks,” Proc. 10th Int'l Conf. High Performance Computing (HiPC '03), Dec. 2003.
[31] J. Rexford, A.G. Greenberg, and F. Bonomi, “Hardware-Efficient Fair Queueing Architectures for High-Speed Networks,” Proc. IEEE INFOCOM '96, vol. 2, pp. 638-646, 1996.
[32] J.W. Roberts, “Virtual Spacing for Flexible Traffic Control,” Int'l J.Comm. Systems, vol. 7, pp. 307-318, 1994.
[33] R. Seifert, Gigabit Ethernet: Technology and Applications for High-Speed LANs. Addison Wesley Longman, 1998.
[34] M. Shreedhar and G. Varghese, “Efficient Fair Queueing Using Deficit Round Robin,” Proc. ACM SIGCOMM '95, pp. 231-242, 1995.
[35] StarGen, StarGen's Merlin Switch, http://www.stargen.com/productsmerlin_switch.shtml , 2004.
[36] D. Stiliadis and A. Varma, “Latency-Rate Servers: A General Model for Analysis of Traffic Scheduling Algorithms,” IEEE/ACM Trans. Networking, 1998.
[37] D. Tutsch and M. Brenner, “MINSimulate—A Multistage Interconnection Network Simulator,” Proc. 17th European Simulation Multiconference: Foundations for Successful Modelling and Simulation (ESM '03), pp. 211-216, 2003.
[38] A. Tyagi, J.K. Muppala, and H. de Meer, “VoIP Support on Differentiated Services Using Expedited Forwarding,” Proc. IEEE Int'l Performance, Computing, and Comm. Conf. (IPCCC '00), Feb. 2000.
[39] Y. Wang and Q. Zhu, “Error Control and Concealment for VideoCommunication: A Review,” Proc. IEEE, vol. 86, no. 5, pp.974-997, May 1998.
17 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool