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Issue No.08 - August (2008 vol.19)
pp: 1086-1098
Modern network processor systems require the ability to adapt their processing capabilities at runtime to changes in network traffic. Traditionally, network processor applications have been optimized for a single static workload scenario, but recently several approaches for runtime adaptation have been proposed. Comparing these approaches and developing novel runtime support algorithms is difficult due to the multicore system-on-a-chip nature of network processors. In this paper, we present a model for network processors that can aid in evaluating different runtime support systems. The model considers workload characteristics of applications and network traffic using a queuing network abstraction. The accuracy of this analytical approach to modeling runtime systems is validated through simulation. We illustrate the effectiveness of our model by comparing the performance of two existing workload adaptation algorithms.
Load balancing and task assignment, Routers
Xin Huang, "Evaluating Dynamic Task Mapping in Network Processor Runtime Systems", IEEE Transactions on Parallel & Distributed Systems, vol.19, no. 8, pp. 1086-1098, August 2008, doi:10.1109/TPDS.2007.70806
[1] J. Allen, B. Bass, C. Basso, R. Boivie, J. Calvignac, G. Davis, L. Frelechoux, M. Heddes, A. Herkersdorf, A. Kind, J. Logan, M. Peyravian, M. Rinaldi, R. Sabhikhi, M. Siegel, and M. Waldvogel, “IBM PowerNP Network Processor: Hardware, Software, and Applications,” IBM J. Research and Development, vol. 47, nos. 2/3, pp. 177-194, 2003.
[2] np7510 10 Gbps Network Processor, AMCC, http:/, 2003.
[3] F. Baskett, K.M. Chandy, R.R. Muntz, and F.G. Palacios, “Open, Closed, and Mixed Networks of Queues with Different Classes of Customers,” J. ACM, vol. 22, no. 2, pp. 248-260, Apr. 1975.
[4] G. Bolch, S. Greiner, H. de Meer, and K.S. Trivedi, Queuing Networks and Markov Chains: Modeling and Performance Evaluation with Computer Science Applications. John Wiley & Sons, Aug. 1998.
[5] J.D. Brutlag, “Aberrant Behavior Detection in Time Series for Network Monitoring,” Proc. Usenix Conf. 14th Systems Administration (LISA '00), pp. 139-146, Dec. 2000.
[6] D. Clark, K. Sollins, J. Wroclawski, D. Katabi, J. Kulik, X. Yang, B. Braden, T. Faber, A. Falk, V. Pingali, M. Handley, and N. Chiappa, “New Arch: Future Generation Internet Architecture,” technical report, Dec. 2003.
[7] P. Crowley and J.-L. Baer, “A Modelling Framework for Network Processor Systems,” Proc. First Network Processor Workshop/Eighth IEEE Int'l Symp. High-Performance Computer Architecture (NP/HPCA '02), pp. 86-96, Feb. 2002.
[8] W. Eatherton, “The Push of Network Processing to the Top of the Pyramid,” Proc. ACM/IEEE Symp. Architectures for Networking and Communication Systems (ANCS '05), Oct. 2005.
[9] NP-1 10-Gigabit 7-Layer Network Processor, EZchip Technologies,, 2002.
[10] M.A. Franklin and S. Datar, “Pipeline Task Scheduling on Network Processors,” Proc. Third Network Processor Workshop/10th IEEE Int'l Symp. High-Performance Computer Architecture (NP/HPCA '04), Feb. 2004.
[11] A. Gavrilovska, K. Schwan, O. Nordstrom, and H. Seifu, “Network Processors as Building Blocks in Overlay Networks,” Proc. 11th Symp. High-Performance Interconnects (HOT-I '03), pp.83-88, Aug. 2003.
[12] S.D. Goglin, D. Hooper, A. Kumar, and R. Yavatkar, “Advanced Software Framework, Tools, and Languages for the IXP Family,” Intel Technology J., vol. 7, no. 4, pp. 64-76, Nov. 2003.
[13] M. Gries, C. Kulkarni, C. Sauer, and K. Keutzer, “Exploring Trade-Offs in Performance and Programmability of Processing Element Topologies for Network Processors,” Proc. Second Network Processor Workshop/Ninth IEEE Int'l Symp. High-Performance Computer Architecture (NP/HPCA '03), pp. 75-87, Feb. 2003.
[14] Intel Second Generation Network Processor, Intel Corp., npfamily/, 2005.
[15] E. Khan, M.W. El-Kharashi, A. Ehtesham Rafiq, F. Gebali, and M. Abd-El-Barr, “Network Processors for Communication Security: A Review,” Proc. IEEE Pacific Rim Conf. Comm., Computers and Signal Processing (PACRIM '03), Feb. 2003.
[16] R. Kokku, T. Riché, A. Kunze, J. Mudigonda, J. Jason, and H. Vin, “A Case for Run-Time Adaptation in Packet Processing Systems,” Proc. Second Workshop Hot Topics in Networks (HOTNETS '03), Nov. 2003.
[17] A. Lakhina, K. Papagiannaki, M. Crovella, C. Diot, E.D. Kolaczyk, and N. Taft, “Structural Analysis of Network Traffic Flows,” SIGMETRICS Performance Evaluation Rev., vol. 32, no. 1, pp. 61-72, June 2004.
[18] R.-T. Liu, N.-F. Huang, C.-H. Chen, and C.-N. Kao, “A Fast String-Matching Algorithm for Network Processor-Based Intrusion Detection System,” Trans. Embedded Computing Systems, vol. 3, no. 3, pp. 614-633, Aug. 2004.
[19] J. Lu and J.J. Wang, “Analytical Performance Analysis of Network-Processor-Based Application Designs,” Proc. 15th Int'l Conf. Computer Comm. and Networks (ICCCN '06), pp. 33-39, Oct. 2006.
[20] G. Memik and W.H. Mangione-Smith, “NEPAL: A Framework for Efficiently Structuring Applications for Network Processors,” Proc. Second Network Processor Workshop/Ninth IEEE Int'l Symp. High-Performance Computer Architecture (NP/HPCA '03), Feb. 2003.
[21] W. Plishker, K. Ravindran, N. Shah, and K. Keutzer, “Automated Task Allocation for Network Processors,” Proc. Network System Design Conf. '04, pp. 235-245, Oct. 2004.
[22] R. Ramaswamy and T. Wolf, “PacketBench: A Tool for Workload Characterization of Network Processing,” Proc. Sixth IEEE Ann. Workshop Workload Characterization (WWC '03), pp. 42-50, Oct. 2003.
[23] L. Ruf, K. Farkas, H. Hug, and B. Plattner, “Network Services on Service Extensible Routers,” Proc. Seventh Ann. Int'l Working Conf. Active Networking (IWAN '05), Nov. 2005.
[24] N. Shah, W. Plishker, and K. Keutzer, “NP-Click: A Programming Model for the Intel IXP1200,” Proc. Second Network Processor Workshop/Ninth IEEE Int'l Symp. High-Performance Computer Architecture (NP/HPCA '03), pp. 100-111, Feb. 2003.
[25] J. Sommers and P. Barford, “Self-Configuring Network Traffic Generation,” Proc. Fourth ACM Internet Measurement Conf. (IMC '04), pp. 68-81, Oct. 2004.
[26] T. Spalink, S. Karlin, L. Peterson, and Y. Gottlieb, “Building a Robust Software-Based Router Using Network Processors,” Proc. 18th ACM Symp. Operating Systems Principles (SOSP '01), pp. 216-229, Oct. 2001.
[27] TejaNP Datasheet, Teja Technologies, http:/, 2003.
[28] L. Thiele, S. Chakraborty, M. Gries, and S. Künzli, “Design Space Exploration of Network Processor Architectures,” Proc. First Network Processor Workshop/Eighth IEEE Int'l Symp. High Performance Computer Architecture (NP/HPCA '02), pp. 30-41, Feb. 2002.
[29] T. Wolf and M. Franklin, “Performance Models for Network Processor Design,” IEEE Trans. Parallel and Distributed Systems, vol. 17, no. 6, pp. 548-561, June 2006.
[30] T. Wolf, N. Weng, and C.-H. Tai, “Design Considerations for Network Processor Operating Systems,” Proc. ACM/IEEE Symp. Architectures for Networking and Comm. Systems (ANCS '05), pp. 71-80, Oct. 2005.
[31] L. Zhao, Y. Luo, L. Bhuyan, and R. Iyer, “Design and Implementation of a Content-Aware Switch Using a Network Processor,” Proc. 13th Int'l Symp. High Performance Interconnects (HOT-I '05), Aug. 2005.
[32] W. Zhou, C. Lin, Y. Li, and Z. Tan, “Queue Management for QoS Provision Build on Network Processor,” Proc. Ninth IEEE Workshop Future Trends of Distributed Computing Systems (FTDCS '03), p.219, May 2003.
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