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A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip
December 2006 (vol. 17 no. 12)
pp. 1377-1389

Abstract—This article proposes a novel O(n) Parallel Banker's Algorithm (PBA), which is a parallelized version of the Banker's Algorithm (BA), a well-known O(m\times n) deadlock avoidance algorithm. We implement the approach in hardware, which we call PBA Unit (PBAU). PBAU is not a mere Verilog HDL translation of BA, but a novel, fully hardware-oriented implementation exploiting maximum hardware parallelism of all computations in BA, resulting in O(1) runtime complexity in the best case and O(n) in the worst. PBAU is an Intellectual Property (IP) block that provides a mechanism of very fast, automatic deadlock avoidance for Multiprocessor System-on-a-Chip (MPSoC), which we predict will be the mainstream of future high performance computing environments. Furthermore, our PBAU supports multiple instance multiple resource systems. We demonstrate that PBAU not only avoids deadlock in a few clock cycles (several orders of magnitude faster than BA in software), but also achieves, in a particular example, a 19 percent speedup of application execution time over avoiding deadlock in software. Lastly, the MPSoC area overhead due to PBAU is small, less than 0.05 percent in our candidate MPSoC example.

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Index Terms:
Parallel Banker's Algorithm, deadlock avoidance in hardware, multiprocessor system-on-a-chip.
Citation:
Jaehwan John Lee, Vincent John Mooney, "A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip," IEEE Transactions on Parallel and Distributed Systems, vol. 17, no. 12, pp. 1377-1389, Dec. 2006, doi:10.1109/TPDS.2006.164
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