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Overall Blocking Behavior Analysis of General Banyan-Based Optical Switching Networks
September 2006 (vol. 17 no. 9)
pp. 1037-1047

Abstract—Banyan networks are attractive for serving as the optical switch architectures due to their nice properties of small depth and absolutely signal loss uniformity. Combining the horizontal expansion and vertical stacking of optical banyan networks is a general scheme for constructing banyan-based optical switching networks. The resulting horizontally expanded and vertically stacked optical banyan (HVOB) networks usually take either a high hardware cost or a large network depth to guarantee the nonblocking property. Blocking behavior analysis is an effective approach to studying network performance and finding a graceful compromise among hardware cost, network depth, and blocking probability; however, little has been done to analyze the blocking behavior of general HVOB networks. In this paper, we study the overall blocking behavior of general HVOB networks, where an upper bound on the blocking probability of a HVOB network is developed with respect to the number of planes (stacked copies) and the number of stages. The upper bound accurately depicts the overall blocking behavior of a HVOB network as verified by an extensive simulation study, and it agrees with the strictly nonblocking condition of the network. The derived upper bound is significant because it reveals the inherent relationship among blocking probability, network depth, and network hardware cost, so that a desirable tradeoff can be made among them. In particular, our bound gives network developers an effective tool to estimate the maximum blocking probability of a HVOB network, in which different routing strategies can be applied with a guaranteed performance in terms of blocking probability, hardware cost and network depth. Our upper bound model predicts some unobvious qualitative behaviors of HVOB networks, and it draws an important conclusion that a very low blocking probability (e.g., less than 0.001 percent) can be achieved in a HVOB network without introducing either a significantly high hardware cost or a large network depth.

[1] Lucent Technologies Press Release, Lucent Technologies' Bell Labs Scientists Set New Fiber Optic Transmission Record, 2002, http://www.lucent.com/press/0302020322.bla.html .
[1] A. Charny, “Providing QoS Guarantees in Input Buffered Crossbar Switches with Speedup,” PhD dissertation, Massachusetts Inst. of Tech nology, Sept. 1998.
[2] H.J. Chao, K.-L. Deng, and Z. Jing, “A Petabit Photonic Switch (p3s),” Proc. IEEE Inforcom'03 Conf., Apr. 2003.
[2] S. Iyer and N. McKeown, “Analysis of the Parallel Packet Switch Architecture,” IEEE/ACM Trans. Networking, vol. 11, no. 2, pp. 314-324, Apr. 2003.
[3] R. Ramaswami and K.N. Sivarajan, Optical Networks: A Practical Perspective. Morgan Kaufmann, 2002.
[3] J. Duncanson, “Inverse Multiplexing,” IEEE Comm. Magazine, vol. 32, no. 4, pp. 34-41, Apr. 1994.
[4] H.S. Hinton, An Introduction to Photonic Switching Fabrics. New York: Plenum, 1993.
[4] P. Fredette, “The Past, Present, and Future of Inverse Multiplexing,” IEEE Comm. Mag., vol. 32, no. 4, pp. 42-46, Apr. 1994.
[5] G.R. Goke and G.J. Lipovski, “Banyan Networks for Partitioning Multiprocessor Systems,” Proc. First Ann. Symp. Computer Architecture, pp. 21-28, 1973.
[5] Inverse Multiplexing for ATM (IMA) Specification, version 1.1, AF-PHY-0086.001, ATM Forum, Mar. 1999.
[6] J.H. Patel, “Performance of Processor-Memory Interconnections for Multiprocessors,” IEEE Trans. Computers, vol. 30, no. 11, pp. 771-780, Oct. 1981.
[6] F.M. Chiussi, D.A. Khotimsky, and S. Krishnan, “Generalized Inverse Multiplexing of Switched ATM Connections,” Proc. IEEE Globecom Conf., pp. 2905-2912, 1998.
[7] C. Kruskal and M. Snir, “The Performance of Multistage Interconnection Networks for Multiprocessors,” IEEE Trans. Comm., vol. 32, pp. 1091-1098, Dec. 1983.
[7] “Inverse Multiplexing over ATM (IMA): A Breakthrough WAN Technology for Corporate Networks,” 3Com Corp., 1997, http://www.mcoecn.org/WhitePapers3COM-Inverse-Multiplexing-ATM. pdf .
[8] F.T. Leighton, Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes. Morgan Kaufmann, 1992.
[8] ATM Switch Router Software Configuration Guide, 12.0(22)W5(25), Cisco Systems, 2004.
[9] M.M. Vaez and C.T. Lea, “Strictly Nonblocking Directional-Coupler-Based Switching Networks under Crosstalk Constraint,” IEEE Trans. Comm., vol. 48, no. 2, pp. 316-323, Feb. 2000.
[9] “Inverse Multiplexing for ATM, Expanding the Revenue Opportunities for Converged Services over ATM,” Lucent Technologies, 2001.
[10] G. Maier and A. Pattavina, “Design of Photonic Rearrangeable Networks with Zero First-Order Switching-Element-Crosstalk,” IEEE Trans. Comm., vol. 49, no. 7, pp. 1268-1279, July 2001.
[10] “Inverse Multiplexing over ATM Works Today,” PMC-Sierra, http://www.electronicstalk.com/news/pmcpmc121.html , 2002.
[11] V.R. Chinni et al., “Crosstalk in a Lossy Directional Coupler Switch,” J. Lightwave Technology, vol. 13, no. 7, pp. 1530-1535, July 1995.
[11] C. Clos, “A Study of Non-Blocking Switching Networks,” Bell System Technical J., pp. 406-424, 1953.
[12] M.M. Vaez and C.T. Lea, “Wide-Sense Nonblocking Banyan-Type Switching Systems Based on Directional Couplers,” IEEE J. Select Areas in Comm., vol. 16, pp. 1327-1332, Sept. 1998.
[12] S. Iyer, “Analysis of a Packet Switch with Memories Running Slower than the Line Rate,” master's thesis, Stanford Univ., May 2000.
[13] T.-S. Wong and C.-T. Lea, “Crosstalk Reduction through Wavelength Assignment in WDM Photonic Switching Networks,” IEEE Trans. Comm., vol. 49, no. 7, pp. 1280-1287, July 2001.
[13] H. Zhang, “Service Disciplines for Guaranteed Performance Service in Packet-Switched Networks,” Proc. IEEE, vol. 83, no. 10, pp. 1374-1396, Oct. 1995.
[14] C.Y. Lee, “Analysis of Switching Networks,” The Bell System Technical J., vol. 34, no. 6, pp. 1287-1315, Nov. 1955.
[14] J. Turner and N. Yamanaka, “Architectural Choices in Large Scale ATM Switches,” IEICE Trans. Comm., vol. E81-B, no. 2, pp. 120-137, Feb. 1998.
[15] C. Jacobaeus, “A Study on Congestion in Link Systems,” Ericsson Technics, vol. 51, no. 3, 1950.
[15] C. Minkenberg, R. Luijten, F. Abel, W. Denzel, and M. Gusat, “Current Issues in Packet Switching Design,” ACM SIGCOMM Computer Comm. Rev., vol. 33, no. 1, pp. 119-124, Jan. 2003.
[16] C. Clos, “A Study of Nonblocking Switching Networks,” The Bell System Technical J., vol. 32, pp. 406-424, 1953.
[16] Y. Mansour and B. Patt-Shamir, “Jitter Control in QoS Networks,” IEEE/ACM Trans. Networking, vol. 9, no. 4, pp. 492-502, Aug. 2001.
[17] D.M. Dias and J.R. Jump, “Analysis and Simulation of Buffered Delta Networks,” IEEE Trans. Computers, vol. 30, no. 4, pp. 273-282, Apr. 1981.
[17] H. Zhang, “Providing End-to-End Performance Guarantees Using Non-Work-Conserving Disciplines,” Computer Comm., vol. 18, no. 10, Oct. 1995.
[18] A. Merchant, “Analytical Models for the Performance of Banyan Networks,” PhD dissertation, Computer Science Dept., Stanford Univ., Calif., 1991.
[18] S. Chuang, A. Goel, N. McKeown, and B. Prabhakar, “Matching Output Queueing with a Combined Input Output Queued Switch,” Proc. IEEE Conf. Computer Comm. (INFOCOM), pp. 1169-1178, 1999.
[19] X. Jiang, H. Shen, M.R. Khandker, and S. Horiguchi, “Blocking Behaviors of Crosstalk-Free Optical Banyan Networks on Vertical Stacking,” IEEE/ACM Trans. Networking, vol. 11, no. 6, pp. 982-993, Dec. 2003.
[19] L. Kleinrock, Queuing Systems, vol. 2. John Wiley & Sons, 1975.
[20] X. Jiang, H. Shen, and S. Horiguchi, “Blocking Probability of Vertically Stacked Optical Banyan Networks under Random Routing,” Proc. GLOBECOM 2003 Conf., Dec. 2003.
[20] P. Krishna, N.S. Patel, A. Charny, and R. Simcoe, “On the Speedup Required for Work-Conserving Crossbar Switches,” IEEE J. Selected Areas in Comm., vol. 17, no. 6, pp. 1057-1066, June 1999.
[21] X. Jiang, P.-H. Ho, and S. Horiguchi, “Performance Modeling of All-Optical Photonic Switches Based on the Vertical Stacking of Banyan Network Structures,” IEEE J. Select Areas in Comm., vol. 23, no. 8, pp. 1620-1631, Aug. 2005.
[21] B. Prabhakar and N. McKowen, “On the Speedup Required for Combined Input and Output Queued Switching,” Automatica, vol. 35, no. 12, pp. 1909-1920, Dec. 1999.
[22] C.-T. Lea, “${\rm {Muti{\hbox{-}}log_2N}}$ Networks and their Applications in High Speed Electronic and Photonic Switching Systems,” IEEE Trans. Comm., vol. 38, pp. 1740-1749, Oct. 1990.
[22] J.S. Turner, “New Directions in Communications (or Which Way to the Information Age?),” IEEE Comm. Magazine, vol. 24, no. 10, pp. 8-15, Oct. 1986.
[23] Y. Mun, Y. Tang, and V. Devarajan, “Analysis of Call Packing and Rearrangement in Multi-Stage Switch,” IEEE Trans. Comm., vol. 42, nos. 2/3/4, pp. 252-254, 1994.
[23] Y. Tamir and H. Chi, “Symmetric Crossbar Arbiters for VLSI Communication Switches,” IEEE Trans. Parallel and Distributed Systems, vol. 4, no. 1, pp. 13-27, Jan. 1993.
[24] M. Hluchyj and M. Karol, “Queueing in High-Performance Packet Switching,” IEEE J. Selected Areas Comm., vol. 6, no. 12, pp. 1587-1597, Dec. 1988.
[25] M. Karol, M. Hluchyj, and S. Morgan, “Input versus Output Queueing on a Space-Division Packet Switch,” IEEE Trans. Comm., vol. 35, no. 12, pp. 1347-1356, Dec. 1987.
[26] S. Iyer, A. Awadallah, and N. McKeown, “Analysis of a Packet Switch with Memories Running at Slower than the Line Rate,” Proc. IEEE Conf. Computer Comm. (INFOCOM), pp. 529-537, 2000.
[27] S. Iyer and N. McKeown, “Making Parallel Packet Switches Practical,” Proc. IEEE Conf. Computer Comm. (INFOCOM), pp. 1680-1687, 2001.
[28] S. Iyer and N. McKeown, “On the Speedup Required for a Multicast Parallel Packet Switch,” IEEE Comm. Letters, vol. 5, no. 6, pp. 269-271, June 2001.
[29] D. Khotimsky and S. Krishnan, “Stability Analysis of a Parallel Packet Switch with Bufferless Input Demultiplexors,” Proc. IEEE Int'l Conf. Comm. (ICC), pp. 100-106, 2001.
[30] D. Khotimsky and S. Krishnan, “Evaluation of Open-Loop Sequence Control Schemes for Multi-Path Switches,” Proc. IEEE Int'l Conf. Comm. (ICC), pp. 2116-2120, May 2002.
[31] A. Aslam and K. Christensen, “A Parallel Packet Switch with Multiplexors Containing Virtual Input Queues,” Computer Comm., vol. 27, no. 13, pp. 1248-1263, 2004.
[32] S. Mneimneh, V. Sharma, and K. Siu, “Switching Using Parallel Input-Output Queued Switches with No Speedup,” IEEE/ACM Trans. Networking, vol. 10, no. 5, pp. 653-665, 2002.
[33] S. Sharif, A. Aziz, and A. Prakash, “An $O(\log^2 N)$ Parallel Algorithm for Output Queuing,” Proc. IEEE Conf. Computer Comm. (INFOCOM), 2002.
[34] A. Prakash, A. Aziz, and V. Ramachandran, “A Near Optimal Schedule for Switch-Memory-Switch Routers,” Proc. ACM Symp. Parallelism in Algorithms and Architectures (SPAA), pp. 343-352, 2003.
[35] A. Prakash, A. Aziz, and V. Ramachandran, “Randomized Parallel Schedulers for Switch-Memory-Switch Routers: Analysis and Numerical Studies,” Proc. IEEE Conf. Computer Comm. (INFOCOM), 2004.
[36] P. Giaccone, E. Leonardi, B. Prabhakar, and D. Shah, “Delay Bounds for Combined Input-Output Switches with Low Speed-Up,” Performance Evaluation, vol. 55, nos. 1-2, pp. 113-128, 2004.
[37] J.Y. LeBoudec, “Network Calculus Made Easy,” Technical Report EPFL-DI 96/218, École Polytechnique Fédérale, Lausanne (EPFL), 1996.
[38] R.L. Cruz, “A Calculus for Network Delay, Part I: Network Elements in Isolation,” IEEE Trans. Information Theory, vol. 37, no. 1, pp. 114-131, Jan. 1991.
[39] H. Attiya and D. Hay, “Randomization Does Not Reduce the Average Delay in Parallel Packet Switches,” Proc. ACM Symp. Parallelism in Algorithms and Architectures (SPAA), pp. 11-20, 2005.
[40] M. Andrews, B. Awerbuch, A. Fernandez, J. Kleinberg, T. Leighton, and Z. Liu, “Universal Stability Results for Greedy Contention-Resolution Protocols,” J. ACM, vol. 48, no. 1, pp. 39-69, 2001.
[41] A. Borodin, J. Kleinberg, P. Raghavan, M. Sudan, and D.P. Williamson, “Adversarial Queueing Theory,” J. ACM, vol. 48, no. 1, pp. 13-38, 2001.
[42] A. Rosen, “A Note on Models for Non-Probabilistic Analysis of Packet Switching Network,” Information Processing Letters, vol. 84, no. 5, pp. 237-240, Dec. 2002.
[43] C. Wu, J. Jiau, and K. Chen, “Characterizing Traffic Behavior and Providing End-to-End Service Guarantees within ATM Networks,” Proc. IEEE Conf. Computer Comm. (INFOCOM), pp. 336-344, 1997.
[44] S. Keshav, An Engineering Approach to Computer Networking. Addison-Wesley, 1997.
[45] H. Zhang and D. Ferrari, “Rate-Controlled Service Disciplines,” J. High Speed Networks, vol. 3, no. 4, pp. 389-412, 1994.

Index Terms:
Optical switching networks, banyan networks, blocking probability, horizontal expansion, vertical stacking.
Citation:
Chen Yu, Xiaohong Jiang, Susumu Horiguchi, Minyi Guo, "Overall Blocking Behavior Analysis of General Banyan-Based Optical Switching Networks," IEEE Transactions on Parallel and Distributed Systems, vol. 17, no. 9, pp. 1037-1047, Sept. 2006, doi:10.1109/TPDS.2006.126
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